公开(公告)号：US08762619B2

公开(公告)日：2014-06-24

申请号：US13010164

申请日：2011-01-20

申请人： Lawrence H. Sasaki ,  David Glen

发明人： Lawrence H. Sasaki ,  David Glen

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/387 ,  H04N21/4104 ,  H04N21/4122 ,  H04N21/422

摘要： A display device that has multiple inputs for receiving video data and peripheral data from multiple computing devices, and an output for attaching a peripheral. The display is operable in one of two states, to provide both a video and peripheral signal paths between a selected one of the interconnected computing devices and the display's panel and attached peripherals. At any given time only one of the computing devices may utilize both the display and any attached peripherals. Exemplary embodiments may handle video and peripheral data streams received from a computing device over a single physical link.

摘要翻译： 一种具有用于从多个计算设备接收视频数据和外围数据的多个输入的显示设备，以及用于附接外围设备的输出。 显示器可操作在两种状态中的一种状态下，以便在互连的计算设备中的所选择的一个与显示器的面板以及连接的外围设备之间提供视频和外围信号路径。 在任何给定时间，只有一个计算设备可以同时使用显示器和任何连接的外围设备。 示例性实施例可以处理通过单个物理链路从计算设备接收的视频和外围数据流。

公开(公告)号：US20120191894A1

公开(公告)日：2012-07-26

申请号：US13010164

申请日：2011-01-20

申请人： Lawrence H. Sasaki ,  David Glen

发明人： Lawrence H. Sasaki ,  David Glen

IPC分类号： G06F13/20

CPC分类号： G06F13/4022 ,  G06F13/387 ,  H04N21/4104 ,  H04N21/4122 ,  H04N21/422

摘要： A display device that has multiple inputs for receiving video data and peripheral data from multiple computing devices, and an output for attaching a peripheral. The display is operable in one of two states, to provide both a video and peripheral signal paths between a selected one of the interconnected computing devices and the display's panel and attached peripherals. At any given time only one of the computing devices may utilize both the display and any attached peripherals. Exemplary embodiments may handle video and peripheral data streams received from a computing device over a single physical link.

摘要翻译： 一种具有用于从多个计算设备接收视频数据和外围数据的多个输入的显示设备，以及用于附接外围设备的输出。 显示器可操作在两种状态中的一种状态下，以便在互连的计算设备中的所选择的一个与显示器的面板以及连接的外围设备之间提供视频和外围信号路径。 在任何给定时间，只有一个计算设备可以同时使用显示器和任何连接的外围设备。 示例性实施例可以处理通过单个物理链路从计算设备接收的视频和外围数据流。

公开(公告)号：US20100218149A1

公开(公告)日：2010-08-26

申请号：US12392332

申请日：2009-02-25

申请人： Lawrence H. Sasaki

发明人： Lawrence H. Sasaki

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： An apparatus for verifying an operation of a hardware descriptor program under test includes a lexical analyzer, a parsing engine and a generator. The lexical analyzer receives input/output (I/O) information of hardware descriptor language code that represents a circuit description of an integrated circuit to be tested. The lexical analyzer performs lexical analysis on the I/O information of the hardware descriptor language code so as to generate a stream of tokens. The parsing engine interprets the stream of tokens representing the I/O information of the hardware descriptor language code based on an interpretation of rules required to test a plurality of functions capable of being executed by the integrated circuit. The generator generates verification module code based on the interpretation of the stream of tokens representing the I/O information of the hardware descriptor language code and the rules interpretation.

摘要翻译： 用于验证被测硬件描述符程序的操作的装置包括词法分析器，解析引擎和生成器。 词汇分析器接收表示要测试的集成电路的电路描述的硬件描述符语言代码的输入/输出（I / O）信息。 词汇分析器对硬件描述符语言代码的I / O信息执行词法分析，以生成令牌流。 解析引擎基于对能够由集成电路执行的多个功能进行测试所需的规则的解释来解释代表硬件描述符语言代码的I / O信息的令牌流。 发生器基于表示硬件描述符语言代码和规则解释的I / O信息的令牌流的解释来生成验证模块代码。

公开(公告)号：US5578943A

公开(公告)日：1996-11-26

申请号：US368945

申请日：1995-01-05

申请人： Lawrence H. Sasaki

发明人： Lawrence H. Sasaki

IPC分类号： H03K19/0175 ,  H04L25/02

CPC分类号： H04L25/029 ,  H03K19/017518 ,  H04L25/0282 ,  H04L25/0294

摘要： An apparatus includes an IC chip with a signal transmitter and an IC chip with a signal receiver, both chips being mounted on a printed circuit board and being connected via conductors on the board. The signal transmitter has a voltage-current converter and a high output impedance current amplifier. The signal receiver has a current-voltage converter. The voltage-current converter converts the voltage of the digital signal to current which in turn is amplified by the high output impedance current amplifier. The amplified current flows via the conductors in the receiver. The digital signal is transferred via the conductors on the current basis. Due to the transmission of the digital signal of current from the signal transmitter to the signal receiver via the conductors, signal spikes while transmitting are reduced and noise immunity is improved. Also, EMI (electromagnetic interference) emission is reduced and power dissipation is small.

摘要翻译： 一种装置包括具有信号发送器的IC芯片和具有信号接收器的IC芯片，两个芯片都安装在印刷电路板上，并通过板上的导体连接。 信号发射器具有电压 - 电流转换器和高输出阻抗电流放大器。 信号接收器具有电流 - 电压转换器。 电压 - 电流转换器将数字信号的电压转换成电流，而电流又被高输出阻抗电流放大器放大。 放大的电流通过接收器中的导体流动。 数字信号通过导线在当前基础上传输。 由于电流从信号发射器经由导体传输到信号接收器的数字信号，传输时的信号尖峰降低，抗噪声能力得到改善。 此外，EMI（电磁干扰）发射减少，功率消耗小。

公开(公告)号：US5382838A

公开(公告)日：1995-01-17

申请号：US33221

申请日：1993-03-18

申请人： Lawrence H. Sasaki ,  Anthony K. D. Brown

发明人： Lawrence H. Sasaki ,  Anthony K. D. Brown

IPC分类号： H03F3/30 ,  H03K5/02 ,  H03K3/01 ,  H03K5/01 ,  H03K17/60 ,  H03K19/08

CPC分类号： H03F3/3001 ,  H03K5/023

摘要： A low power (10 mW), high-speed (50 Mb/s) digital driver is formed from three analogue components: level shifter to limit the output swing, waveshaper to limit the slew-rate of the output transition, and a Class AB output stage to buffer the signal. The components afford flexibility to meet the demands of different applications. The driver can be limited to 1V swing for terminated applications such as for backplanes, or it can be limited to 1V swing for unterminated applications such as intraboard (PCB) communication.

摘要翻译： 低功耗（10 mW），高速（50 Mb / s）数字驱动器由三个模拟组件组成：电平转换器，用于限制输出摆幅，波形以限制输出转换的转换速率，以及一个AB类 输出级缓冲信号。 这些组件提供灵活性以满足不同应用的需求。 驱动器可以限制为1V摆幅，用于终端应用，如用于背板，或者可以限制为1V摆动，用于未端接的应用，如内部（PCB）通信。

公开(公告)号：US08296693B2

公开(公告)日：2012-10-23

申请号：US12392332

申请日：2009-02-25

申请人： Lawrence H. Sasaki

发明人： Lawrence H. Sasaki

IPC分类号： G06F17/50 ,  G06F9/44

CPC分类号： G06F17/5022

摘要： An apparatus for verifying an operation of a hardware descriptor program under test includes a lexical analyzer, a parsing engine and a generator. The lexical analyzer receives input/output (I/O) information of hardware descriptor language code that represents a circuit description of an integrated circuit to be tested. The lexical analyzer performs lexical analysis on the I/O information of the hardware descriptor language code so as to generate a stream of tokens. The parsing engine interprets the stream of tokens representing the I/O information of the hardware descriptor language code based on an interpretation of rules required to test a plurality of functions capable of being executed by the integrated circuit. The generator generates verification module code based on the interpretation of the stream of tokens representing the I/O information of the hardware descriptor language code and the rules interpretation.

摘要翻译： 用于验证被测硬件描述符程序的操作的装置包括词法分析器，解析引擎和生成器。 词汇分析器接收表示要测试的集成电路的电路描述的硬件描述符语言代码的输入/输出（I / O）信息。 词汇分析器对硬件描述符语言代码的I / O信息执行词法分析，以生成令牌流。 解析引擎基于对能够由集成电路执行的多个功能进行测试所需的规则的解释来解释代表硬件描述符语言代码的I / O信息的令牌流。 发生器基于表示硬件描述符语言代码和规则解释的I / O信息的令牌流的解释来生成验证模块代码。

公开(公告)号：US5063579A

公开(公告)日：1991-11-05

申请号：US524398

申请日：1990-05-11

申请人： Lawrence H. Sasaki ,  Sun-Shiu D. Chan

发明人： Lawrence H. Sasaki ,  Sun-Shiu D. Chan

IPC分类号： H03K23/48 ,  H03K23/50 ,  H03K23/64 ,  H03K23/66 ,  H03K23/68 ,  H03L7/197

CPC分类号： H03K23/507 ,  H03K23/667 ,  H03K23/68

摘要： A scaler comprising a plurality of flip-flops, varies its frequency division to correct phase by 0.5 clock cycle. Each flip-flop is continuously and synchronously responsive to either a rising or a falling edge of the clock pulses. Normally, the scaler's state transits along one of two loops, which generate output pulses having identical repetition rates. When a control signal is applied, the scaler's state transits from one loop to the other, generating at least one output at an alternative repetition rate. The alternative repetition rate is either lower or higher than the identical repetition rate by an integral number of half cycles of the input clock pulses. Where there are two control signals, a lower or higher alternative repetition rate can be selected. Since the flip-flops are responsive to either edge of the clock pulses without clock gating interruptions, there is no jitter and the scaler's robustness is improved. Also the clock frequency can be effectively halved.

摘要翻译： 包括多个触发器的缩放器改变其分频，以校正相位0.5个时钟周期。 每个触发器连续地和同步地响应于时钟脉冲的上升沿或下降沿。 通常，缩放器的状态沿着两个循环中的一个循环，其产生具有相同重复率的输出脉冲。 当施加控制信号时，缩放器的状态从一个循环转移到另一个循环，以替代的重复率产生至少一个输出。 替代重复率低于或高于相同的重复率乘以输入时钟脉冲的半个周期的整数倍。 在有两个控制信号的情况下，可以选择较低或更高的替代重复率。 由于触发器响应于时钟脉冲的任一边沿而没有时钟选通中断，所以没有抖动，并且缩放器的稳健性得到改善。 此外，时钟频率可以有效地减半。

公开(公告)号：US5578944A

公开(公告)日：1996-11-26

申请号：US542492

申请日：1995-10-13

申请人： Lawrence H. Sasaki

发明人： Lawrence H. Sasaki

IPC分类号： H03K19/0175 ,  H04L25/02

CPC分类号： H04L25/029 ,  H03K19/017518 ,  H04L25/0282 ,  H04L25/0294

摘要： An apparatus includes an IC chip with a signal transmitter and an IC chip with a signal receiver, both chips being mounted on a printed circuit board and being connected via conductors on the board. The signal transmitter has a voltage-current converter and a high output impedance current amplifier. The signal receiver has a current-voltage converter. The voltage-current converter converts the voltage of the digital signal to current which in turn is amplified by the high output impedance current amplifier. The amplified current flows via the conductors in the receiver. The digital signal is transferred via the conductors on the current basis. Due to the transmission of the digital signal of current from the signal transmitter to the signal receiver via the conductors, signal spikes while transmitting are reduced and noise immunity is improved. Also, EMI (electromagnetic interference) emission is reduced and power dissipation is small.

摘要翻译： 一种装置包括具有信号发送器的IC芯片和具有信号接收器的IC芯片，两个芯片都安装在印刷电路板上，并通过板上的导体连接。 信号发射器具有电压 - 电流转换器和高输出阻抗电流放大器。 信号接收器具有电流 - 电压转换器。 电压 - 电流转换器将数字信号的电压转换成电流，而电流又被高输出阻抗电流放大器放大。 放大的电流通过接收器中的导体流动。 数字信号通过导线在当前基础上传输。 由于电流从信号发射器经由导体传输到信号接收器的数字信号，传输时的信号尖峰降低，抗噪声能力得到改善。 此外，EMI（电磁干扰）发射减少，功率消耗小。

公开(公告)号：US4646289A

公开(公告)日：1987-02-24

申请号：US678883

申请日：1984-12-06

申请人： Nicholas Tsiakas ,  Stephen K. Sunter ,  Ronald G. Wellard ,  Lawrence H. Sasaki

发明人： Nicholas Tsiakas ,  Stephen K. Sunter ,  Ronald G. Wellard ,  Lawrence H. Sasaki

IPC分类号： H04L5/14 ,  H04B3/04 ,  H04J3/00 ,  H04J3/04 ,  H04L12/413 ,  H04M9/00 ,  H04M11/06 ,  H04M13/00 ,  H04Q3/58 ,  H04J3/12

CPC分类号： H04L12/40013 ,  H04L12/413 ,  H04M11/06 ,  H04M9/008 ,  H04L12/40163

摘要： Bidirectional communication of voice and data signals over a two wire telephone line interconnecting several telephone sets with a digital access circuit of a central data and voice communication facility is achieved by a frequency division multiplexing circuit that functions either as a set interface for a telephone or as a line card interface for the access circuit. Data message signals input to the multiplexing circuit are stored in a shift register for subsequent modulation of a carrier signal, but since only one interface may enter a transmission mode at one time transmission priority is assigned by a controller to the interface that first attempts transmission on an inactive line. All other interface then enter a monitor mode to listen but not act on the transmitted message. Transmission errors caused by line noise, or collision transmissions between two or more interfaces are resolved via message transactions between the interfaces only, and retransmission priority is resolved in favor of an interface having the lowest address. Controllable transmit and receive equalizers define analog signal paths in the interfaces and compensate for line losses.

摘要翻译： 通过将多个电话机与中央数据和语音通信设施的数字接入电路互连的双线电话线的语音和数据信号的双向通信是通过频分复用电路来实现的，频分复用电路作为电话机的设置接口或者作为 用于接入电路的线路卡接口。 输入到多路复用电路的数据信息信号存储在移位寄存器中用于后续的载波信号的调制，但由于只有一个接口可以一次进入传输模式，控制器将传输优先级分配给首先尝试发送的接口 一个不活动的行。 所有其他接口然后进入监听模式，以侦听而不对所发送的消息采取行动。 由线路噪声或两个或多个接口之间的冲突传输引起的传输错误仅通过接口之间的消息事务来解决，重传优先级被解析为有利于具有最低地址的接口。 可控发送和接收均衡器定义接口中的模拟信号路径，并补偿线路损耗。