公开(公告)号：US4646289A

公开(公告)日：1987-02-24

申请号：US678883

申请日：1984-12-06

申请人： Nicholas Tsiakas ,  Stephen K. Sunter ,  Ronald G. Wellard ,  Lawrence H. Sasaki

发明人： Nicholas Tsiakas ,  Stephen K. Sunter ,  Ronald G. Wellard ,  Lawrence H. Sasaki

IPC分类号： H04L5/14 ,  H04B3/04 ,  H04J3/00 ,  H04J3/04 ,  H04L12/413 ,  H04M9/00 ,  H04M11/06 ,  H04M13/00 ,  H04Q3/58 ,  H04J3/12

CPC分类号： H04L12/40013 ,  H04L12/413 ,  H04M11/06 ,  H04M9/008 ,  H04L12/40163

摘要： Bidirectional communication of voice and data signals over a two wire telephone line interconnecting several telephone sets with a digital access circuit of a central data and voice communication facility is achieved by a frequency division multiplexing circuit that functions either as a set interface for a telephone or as a line card interface for the access circuit. Data message signals input to the multiplexing circuit are stored in a shift register for subsequent modulation of a carrier signal, but since only one interface may enter a transmission mode at one time transmission priority is assigned by a controller to the interface that first attempts transmission on an inactive line. All other interface then enter a monitor mode to listen but not act on the transmitted message. Transmission errors caused by line noise, or collision transmissions between two or more interfaces are resolved via message transactions between the interfaces only, and retransmission priority is resolved in favor of an interface having the lowest address. Controllable transmit and receive equalizers define analog signal paths in the interfaces and compensate for line losses.

摘要翻译： 通过将多个电话机与中央数据和语音通信设施的数字接入电路互连的双线电话线的语音和数据信号的双向通信是通过频分复用电路来实现的，频分复用电路作为电话机的设置接口或者作为 用于接入电路的线路卡接口。 输入到多路复用电路的数据信息信号存储在移位寄存器中用于后续的载波信号的调制，但由于只有一个接口可以一次进入传输模式，控制器将传输优先级分配给首先尝试发送的接口 一个不活动的行。 所有其他接口然后进入监听模式，以侦听而不对所发送的消息采取行动。 由线路噪声或两个或多个接口之间的冲突传输引起的传输错误仅通过接口之间的消息事务来解决，重传优先级被解析为有利于具有最低地址的接口。 可控发送和接收均衡器定义接口中的模拟信号路径，并补偿线路损耗。

公开(公告)号：US06895535B2

公开(公告)日：2005-05-17

申请号：US10727583

申请日：2003-12-05

申请人： Stephen K. Sunter ,  Aubin P. J. Roy

发明人： Stephen K. Sunter ,  Aubin P. J. Roy

IPC分类号： G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/00 ,  G01R31/08

CPC分类号： G01R31/2834 ,  G01R31/2884 ,  G01R31/3171 ,  G01R31/31725 ,  G01R31/318577 ,  G01R31/31858 ,  G01R31/318594

摘要： A circuit and method are described in which a DC voltage or current is connected to a high frequency, AC-coupled signal path between a transmitter and a receiver, and the bit error rate of the data transmission is tested while applying an altered bias voltage to the received signal. The bias voltage can be connected via a resistor, inductor or transistors. The transmitted signal is attenuated resistively, and a load capacitance is applied whose value causes digital transition times to exceed one unit interval. An intended application is testing of an integrated circuit, serializer/deserializer (serdes) operating above 1 GHz.

摘要翻译： 描述了一种电路和方法，其中直流电压或电流连接到发射机和接收机之间的高频交流耦合信号路径，并且在施加改变的偏置电压的同时测试数据传输的误码率 接收信号。 偏置电压可以通过电阻，电感或晶体管连接。 发送的信号被电阻衰减，并且施加负载电容，其值导致数字转换时间超过一个单位间隔。 预期的应用是测试在1 GHz以上运行的集成电路，串行器/解串器（Serdes）。

公开(公告)号：US5349587A

公开(公告)日：1994-09-20

申请号：US858377

申请日：1992-03-26

申请人： Benoit Nadeau-Dostie ,  Abu S. M. Hassan ,  Dwayne M. Burek ,  Stephen K. Sunter

发明人： Benoit Nadeau-Dostie ,  Abu S. M. Hassan ,  Dwayne M. Burek ,  Stephen K. Sunter

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/24 ,  A04B17/00

CPC分类号： G01R31/31858 ,  G01R31/318552 ,  G06F11/24

摘要： In methods and apparatus for testing a digital system, scannable memory elements of the digital system are configured in a scan mode in which the memory elements are connected to define a plurality of scan chains. A test stimulus pattern is clocked into each of the scan chains at a respective clock rate, at least two of the clock rates being different from one another. The memory elements of each scan chain are then configured in a normal operation mode in which the memory elements are interconnected by the combinational network for at least one clock cycle at a highest of the respective clock rates. The memory elements are then reconfigured in the scan mode, and a test response pattern is clocked out of each of the scan chains at its respective clock rate. The methods and apparatus are particularly useful for testing digital systems such as digital integrated circuits in which different memory elements are clocked at different rates during normal operation.

摘要翻译： 在用于测试数字系统的方法和装置中，数字系统的可扫描存储器元件被配置成扫描模式，其中存储器元件被连接以限定多个扫描链。 以相应的时钟速率将测试刺激图案计时到每个扫描链中，至少两个时钟速率彼此不同。 每个扫描链的存储器元件然后被配置为正常操作模式，其中存储器元件通过组合网络互连至少一个时钟周期，在相应时钟速率的最高处。 然后在扫描模式中重新配置存储器元件，并且以各自的时钟速率从每个扫描链中计时测试响应模式。 所述方法和装置对于测试诸如数字集成电路的数字系统特别有用，其中在正常操作期间不同的存储器元件以不同的速率被定时。

公开(公告)号：US06703820B2

公开(公告)日：2004-03-09

申请号：US10300620

申请日：2002-11-21

申请人： Stephen K. Sunter

发明人： Stephen K. Sunter

IPC分类号： G01R1314

CPC分类号： G01R31/3167

摘要： A sampling circuit for use in testing an analog waveform includes a sampling switch for sampling an analog waveform, a sample storage capacitance including a single capacitance and a plurality of capacitances selectably connected in parallel; and a sampling pulse generating circuit.

摘要翻译： 用于测试模拟波形的采样电路包括用于对模拟波形进行采样的采样开关，包括单个电容的采样存储电容和可并联选择地并联的多个电容; 和采样脉冲发生电路。

公开(公告)号：US06567971B1

公开(公告)日：2003-05-20

申请号：US10021810

申请日：2001-12-20

申请人： Walter H. Banzhaf ,  Aubin P. J. Roy ,  Stephen K. Sunter

发明人： Walter H. Banzhaf ,  Aubin P. J. Roy ,  Stephen K. Sunter

IPC分类号： G06F1750

CPC分类号： G06F17/5045

摘要： A method of synthesizing a circuit employs a technology parameter extraction circuit which is synthesized with constraints and simulated to derive values of performance parameters, and then, based on the derived values, a predetermined high-level circuit description of a second circuit is modified and then synthesized using the same constraints. Optional steps include the creation and substitution of a sub-circuit model to permit correct simulation, or substitution of an alternative sub-circuit to synthesize a second circuit that cannot otherwise be synthesized directly.

摘要翻译： 合成电路的方法采用技术参数提取电路，该技术参数提取电路采用约束条件合成并进行仿真，得出性能参数值，然后根据导出值修改第二电路的预定高电平电路描述， 使用相同的约束合成。 可选的步骤包括创建和替换子电路模型以允许正确的模拟，或替代替代子电路以合成否则不能直接合成的第二电路。

公开(公告)号：US06492798B2

公开(公告)日：2002-12-10

申请号：US09842700

申请日：2001-04-27

申请人： Stephen K. Sunter

发明人： Stephen K. Sunter

IPC分类号： G01R1334

CPC分类号： G01R31/3167

摘要： A method of testing an analog, or mixed analog and digital, circuit designed for operation at a clock frequency multiplexes a plurality of low frequency stimulus signals using a high frequency clock to produce a circuit input signal, applies the input signal to the circuit to obtain a circuit output signal; samples the circuit output signal synchronously with the high frequency clock at a frequency equal to the clock frequency divided by the number of the low frequency signals; stores the samples and measures properties of the signal samples to determine properties of the output signal of the circuit.

摘要翻译： 一种测试设计用于在时钟频率下操作的模拟或混合模拟和数字电路的方法，其使用高频时钟多路复用多个低频激励信号以产生电路输入信号，将输入信号施加到电路以获得 电路输出信号; 以与时钟频率相等的频率除以低频信号的数量，与高频时钟同步地对电路输出信号进行采样; 存储样本并测量信号样本的属性，以确定电路的输出信号的特性。

公开(公告)号：US07159159B2

公开(公告)日：2007-01-02

申请号：US10414309

申请日：2003-04-16

申请人： Stephen K. Sunter

发明人： Stephen K. Sunter

IPC分类号： G01R31/28

CPC分类号： G01R31/3167 ,  G01R31/3012 ,  G01R31/318533

摘要： A boundary scan cell for use in a circuit having a boundary scan shift register (BSSR) having boundary scan cells associated with pins of the circuit, the cell having a single-bit shift register element and an associated update latch, comprises a logic circuit for controlling the logic state of an associated pin, analog switches connecting the associated pin to analog test buses, and logic circuitry for selectively configuring the cell in a parametric test mode in which the cell shift register element controls the analog switches, and in a digital test mode in which the cell shift register element controls the logic state of the associated pin.

摘要翻译： 一种边界扫描单元，用于具有边界扫描移位寄存器（BSSR）的电路，边界扫描移位寄存器（BSSR）具有与电路的引脚相关联的边界扫描单元，该单元具有单位移位寄存器元件和相关联的更新锁存器， 控制相关引脚的逻辑状态，将相关引脚连接到模拟测试总线的模拟开关和用于在参数测试模式中选择性地配置单元的逻辑电路，其中单元移位寄存器元件控制模拟开关，并且在数字测试 模式，其中单元移位寄存器元件控制相关引脚的逻辑状态。

公开(公告)号：US4797580A

公开(公告)日：1989-01-10

申请号：US114552

申请日：1987-10-29

申请人： Stephen K. Sunter

发明人： Stephen K. Sunter

IPC分类号： H03K19/003 ,  H03K19/096 ,  H03K17/16 ,  H03K19/017 ,  H03K19/094

CPC分类号： H03K19/00361 ,  H03K19/0963

摘要： Current-mirror circuitry is utilized on a MOS integrated circuit for regulating the amount of current entering the pre-charged nodes of a pre-charged logic circuit. The current-mirror circuitry involves a series of bias transistors, each extending in parallel with a respective one of the pre-charge transistors, and a bias current circuit. The bias current circuit is formed by a transistor and a resistance element which are serially connected across the power supply of the logic circuit. The gate of the bias circuit transistor is connected to the gates of the bias transistors, and the current passing through each bias transistor depends upon the relative dimensions between that transistor and the respective bias circuit transistor. The value of the resistance element determines the amount of current passing through the bias circuit transistor and therefore through the bias transistors.

摘要翻译： 电流镜电路用于MOS集成电路，用于调节进入预充电逻辑电路的预充电节点的电流量。 电流镜电路涉及一系列偏置晶体管，每个偏置晶体管与预充电晶体管中的相应一个并联延伸，以及偏置电流电路。 偏置电流电路由串联在逻辑电路的电源上的晶体管和电阻元件形成。 偏置电路晶体管的栅极连接到偏置晶体管的栅极，并且通过每个偏置晶体管的电流取决于该晶体管和相应的偏置电路晶体管之间的相对尺寸。 电阻元件的值确定通过偏置电路晶体管并因此通过偏置晶体管的电流量。

公开(公告)号：US4659948A

公开(公告)日：1987-04-21

申请号：US514443

申请日：1983-07-18

申请人： Stephen K. Sunter ,  Yachin Afek

发明人： Stephen K. Sunter ,  Yachin Afek

IPC分类号： H03K19/096 ,  H03K17/693 ,  H03K19/177 ,  H03K19/173 ,  H03K19/20

CPC分类号： H03K17/693 ,  H03K19/1772

摘要： A single plane programmable logic array (PLA) using dynamic CMOS logic has switching transistors located at specific locations within a row-column matrix. The transistors within a column are series connected and have their gates common connected in rows. PMOS and NMOS control transistors conduct exclusively to connect output and input ends of the columns respectively to logic 1 or logic 0 in successive phases of a common clock. Control inputs are applied to specific rows. By applying data inputs to column input ends and interconnecting all the column output ends, the PLA is configured to function as a multiplexer. By setting the input end of columns to logic 0 and selectively interconnecting output ends of the columns, the PLA is configured to perform other combinational logic functions.

摘要翻译： 使用动态CMOS逻辑的单平面可编程逻辑阵列（PLA）具有位于行列矩阵内的特定位置处的开关晶体管。 列内的晶体管是串联连接的，并且它们的栅极共同连接成行。 PMOS和NMOS控制晶体管专门用于将列的输出和输入端分别连接到公共时钟的连续相位中的逻辑1或逻辑0。 控制输入​​应用于特定行。 通过将数据输入应用于列输入端并互连所有列输出端，PLA被配置为用作多路复用器。 通过将列的输入端设置为逻辑0并选择性地互连列的输出端，PLA被配置为执行其他组合逻辑功能。

公开(公告)号：US07453255B2

公开(公告)日：2008-11-18

申请号：US10991365

申请日：2004-11-19

申请人： Stephen K. Sunter ,  Aubin P. J. Roy

发明人： Stephen K. Sunter ,  Aubin P. J. Roy

IPC分类号： G06M1/10 ,  G06F1/04

CPC分类号： G01R29/26 ,  G01R31/31709

摘要： A method and circuit for measuring a time interval between transitions of periodic signals at nodes of a circuit-under-test (CUT), the signals having a periodic clock frequency, the method includes periodically latching a digital value of a first periodic signal at edges of an undersampling clock, simultaneously periodically latching a digital value of a second periodic signal at edges of the undersampling clock, combining the latched digital values of the first and second periodic signals to produce a combined output whose duty cycle is proportional to the time interval between a median edge of latched digital values of the first periodic signal and a median edge of latched digital values of the second periodic signal; and counting the number of undersampling clock cycles in which the combined output is a predetermined logic value within a predetermined time interval whereat the number is proportional to a time interval between a transition of the first periodic signal and a transition of the second periodic signal.

摘要翻译： 一种用于测量在被测电路（CUT）的节点处的周期信号的转变之间的时间间隔的方法和电路，所述信号具有周期性时钟频率，所述方法包括周期性地锁存边缘处的第一周期信号的数字值 同时在欠采样时钟的边缘周期性地锁存第二周期信号的数字值，组合第一和第二周期信号的锁存数字值，以产生其占空比与时间间隔成比例的组合输出 第一周期信号的锁存数字值的中间边缘和第二周期信号的锁存数字值的中间边沿; 以及在预定时间间隔内对组合输出是预定逻辑值的欠采样时钟周期的数目进行计数，其中数字与第一周期信号的转变与第二周期信号的转变之间的时间间隔成比例。