公开(公告)号：US5572695A

公开(公告)日：1996-11-05

申请号：US250974

申请日：1994-05-31

申请人： Lawrence P. Andrews ,  Derrick L. Arias ,  Judith M. Linger ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi

发明人： Lawrence P. Andrews ,  Derrick L. Arias ,  Judith M. Linger ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi

IPC分类号： G06F15/16 ,  G06F12/02 ,  G06F15/167

CPC分类号： G06F12/0284 ,  H04Q2213/13103 ,  H04Q2213/13107 ,  H04Q2213/1332 ,  H04Q2213/13396

摘要： A digital signal processing system includes first and second logical memory mapping units coupled to first and second digital processors respectively and to a data storage unit. The system further includes first and second mapping registers for containing first and second address mapping information coupled to the first and second digital processors respectively. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.

摘要翻译： 数字信号处理系统包括分别耦合到第一和第二数字处理器的第一和第二逻辑存储器映射单元以及数据存储单元。 该系统还包括第一和第二映射寄存器，用于分别包含耦合到第一和第二数字处理器的第一和第二地址映射信息。 第一和第二映射单元用于分别接收（i）分别由第一和第二数字处理器生成的第一和第二逻辑地址，以及（ii）第一和第二地址映射信息，并且生成第一和第二物理地址， 数字处理器可以独立地访问数据存储单元内的多个存储器位置中的任何一个。

公开(公告)号：US5553293A

公开(公告)日：1996-09-03

申请号：US353016

申请日：1994-12-09

申请人： Lawrence P. Andrews ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi ,  Kevin B. Williams ,  Christopher D. Touch

发明人： Lawrence P. Andrews ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi ,  Kevin B. Williams ,  Christopher D. Touch

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An interprocessor interrupt hardware unit ("IIU") for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off loads tasks involved in processing interrupts from the operating kernel of the remote processor. Control blocks of interrupt information and commands are stored in Data Random Access Memory (DRAM) by the remote processor. The remote processor sets up a buffer of control block memory addresses in DRAM for the IIU to access to retrieve the control blocks from DRAM. The IIU retrieves a control block and loads the control block into registers. The IIU then issues an interrupt request to the host processor. The host processor receives the interrupt request and reads the registers to obtain the control block. The host processor clears the interrupt request and indicates to the IIU that the interrupt has been processed. The IIU then notifies the remote processor that the interrupt has been processed. The IIU may be programmed to notify the remote processor of completion either by an interrupt or by setting a status flag in the DRAM.

摘要翻译： 处理器中断硬件单元（“IIU”），用于处理多处理器系统上的远程处理器和主机处理器之间的中断。 IIU负载处理来自远程处理器的操作内核的中断的任务。 中断信息和命令的控制块由远程处理器存储在数据随机存取存储器（DRAM）中。 远程处理器在DRAM中设置控制块存储器地址的缓冲器，用于IIU以访问以从DRAM中检索控制块。 IIU检索一个控制块，并将控制块加载到寄存器中。 然后，IIU向主机处理器发出中断请求。 主机处理器接收中断请求并读取寄存器以获取控制块。 主处理器清除中断请求，并向IIU指示中断已被处理。 然后，IIU通知远处理器中断已被处理。 IIU可以被编程为通过中断或通过在DRAM中设置状态标志来通知远程处理器完成。

公开(公告)号：US5634099A

公开(公告)日：1997-05-27

申请号：US352953

申请日：1994-12-09

申请人： Lawrence P. Andrews ,  Derrick Arias ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi ,  Kevin B. Williams

发明人： Lawrence P. Andrews ,  Derrick Arias ,  Baiju D. Mandalia ,  Oscar E. Ortega ,  John C. Sinibaldi ,  Kevin B. Williams

IPC分类号： G06F13/28 ,  G06F15/17

CPC分类号： G06F13/28

摘要： There is provided a Direct Access Memory Unit (DAu) that is associated with a remote processor module in a multi-processing system. The DAU performs Direct Memory Access (DMA) operations independently of a Central Processing Unit (CPU) in the remote processor module. The CPU requests a DMA by writing information relevant to the DMA to the remote processor's memory. The address of each control block is written to a circular queue, also in the remote processor's memory. The DAU determines if there are any control blocks to process and if so, the DAU will perform the DMA operation (reading data from or writing data to the memory of the host processor), all without the intervention of the CPU of the remote processor module. The CPU adds a new control block by loading its address in a location in the circular queue that is ahead of the circular queue location that the DAU is processing. The CPU can abort a pending DMA request during DAU operations by setting a skip bit in the control block. Upon the completion of performing a DMA request, the DAU will set a complete bit in the control block in the remote processor's memory. An interrupt can also be sent to the CPU, wherein the CPU is advised that a DMA request has been completed. The data in a DMA operation is sent in bursts to a buffer located between two busses having different data transmission rates.

摘要翻译： 提供了与多处理系统中的远程处理器模块相关联的直接存取存储器单元（DAu）。 DAU独立于远程处理器模块中的中央处理器（CPU）执行直接存储器访问（DMA）操作。 CPU通过将与DMA有关的信息写入远程处理器的内存来请求DMA。 每个控制块的地址也写入循环队列，也在远程处理器的内存中。 DAU确定是否有任何控制块进行处理，如果是这样，则DAU将执行DMA操作（从主机处理器的存储器读取数据或向主机处理器写入数据），而无需远程处理器模块的CPU的干预 。 CPU通过将其地址加载到循环队列中位于DAU正在处理的循环队列位置之前的位置来添加新的控制块。 CPU可以在DAU操作期间通过设置控制块中的跳过位来中止待处理的DMA请求。 在执行DMA请求完成后，DAU将在远程处理器的存储器中的控制块中设置完整的位。 中断也可以发送到CPU，其中建议CPU已经完成了DMA请求。 DMA操作中的数据以突发方式发送到位于具有不同数据传输速率的两个总线之间的缓冲器。

公开(公告)号：US4991169A

公开(公告)日：1991-02-05

申请号：US227832

申请日：1988-08-02

申请人： Gordon T. Davis ,  Michael G. Ho Lung ,  Baiju D. Mandalia ,  Roland J. Millas ,  Oscar E. Ortega ,  Rafael J. Picon ,  Loran R. Queen ,  Richard H. Robinson ,  William R. Robinson, Jr. ,  Leo A. Sharp, Jr. ,  Jan W. van den Berg

发明人： Gordon T. Davis ,  Michael G. Ho Lung ,  Baiju D. Mandalia ,  Roland J. Millas ,  Oscar E. Ortega ,  Rafael J. Picon ,  Loran R. Queen ,  Richard H. Robinson ,  William R. Robinson, Jr. ,  Leo A. Sharp, Jr. ,  Jan W. van den Berg

IPC分类号： H04M11/06 ,  H04J3/12

CPC分类号： H04J3/12 ,  H04Q2213/13034 ,  H04Q2213/1309 ,  H04Q2213/13103 ,  H04Q2213/13107 ,  H04Q2213/13174 ,  H04Q2213/13199 ,  H04Q2213/13213 ,  H04Q2213/13215 ,  H04Q2213/13292 ,  H04Q2213/13377 ,  H04Q2213/13396

摘要： A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the most processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions. The DSP may also perform processing services in order to reduce the processing burden on the host system (e.g. parity checking of data, detection of specific character functions in data or specific tones in audio signals, selective routing of voice to host storage for voice mail applications, etc.).