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    METHODS FOR NORMALIZING STRAIN IN A SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHODS FOR NORMALIZING STRAIN IN A SEMICONDUCTOR DEVICE 有权
    用于在半导体器件中正常化应变的方法

    公开(公告)号：US20090246920A1

    公开(公告)日：2009-10-01

    申请号：US12057072

    申请日：2008-03-27

    申请人： Lee Wee Teo ,  Chung Foong Tan ,  Alain Chan ,  Elgin Kiok Boone Quek

    发明人： Lee Wee Teo ,  Chung Foong Tan ,  Alain Chan ,  Elgin Kiok Boone Quek

    IPC分类号： H01L21/8232

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

    摘要： The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.

    摘要翻译： 通过根据器件的种群密度选择性地将应变诱导结构与半导体器件的受影响区域分离开，使得在半导体器件中诱导应变的电性能增强效应通过具有变化的器件部件的种群密度的衬底基本上均匀 组件。 通过在诸如MOS晶体管栅电极的器件部件上选择性地形成侧壁间隔而获得不同的间隔距离，其中侧壁间隔物在具有相对较高密度的器件部件的区域中具有相对较小的宽度，并且具有 相对低密度的器件组件。 通过改变应变诱导结构与受影响部件的分离距离，在集成电路中的器件的各种部件中获得均匀的电性能，而不管部件群体密度如何。

    Methods for normalizing strain in a semiconductor device
    2.
    发明授权
    Methods for normalizing strain in a semiconductor device 有权
    在半导体器件中归一化应变的方法

    公开(公告)号：US07816274B2

    公开(公告)日：2010-10-19

    申请号：US12057072

    申请日：2008-03-27

    申请人： Lee Wee Teo ,  Chung Foong Tan ,  Alain Chan ,  Elgin Kiok Boone Quek

    发明人： Lee Wee Teo ,  Chung Foong Tan ,  Alain Chan ,  Elgin Kiok Boone Quek

    IPC分类号： H01L21/302

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

    摘要： The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the effected regions of the semiconductor devices depending upon the population density of device components. Differing separation distances are obtained by selectively forming sidewall spacers on device components, such as MOS transistor gate electrodes, in which the sidewall spacers have a relatively small width in regions having a relatively high density of device components, and a relatively larger width in regions having a relatively low density of device components. By varying the separation distance of strain-inducing structures from the effected components, uniform electrical performance is obtained in the various components of the devices in an integrated circuit regardless of the component population density.

    摘要翻译： 通过根据器件的种群密度选择性地将应变诱导结构与半导体器件的受影响区域分离开，使得在半导体器件中诱导应变的电性能增强效应通过具有变化的器件部件的种群密度的衬底基本上均匀 组件。 通过在诸如MOS晶体管栅电极的器件部件上选择性地形成侧壁间隔而获得不同的间隔距离，其中侧壁间隔物在具有相对较高密度的器件部件的区域中具有相对较小的宽度，并且具有 相对低密度的器件组件。 通过改变应变诱导结构与受影响部件的分离距离，在集成电路中的器件的各种部件中获得均匀的电性能，而不管部件群体密度如何。

    PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING EMBEDDED EPITAXIAL REGIONS
    3.
    发明申请
    PROCESS FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING EMBEDDED EPITAXIAL REGIONS 有权
    用于制造具有嵌入式外延区域的半导体器件的工艺

    公开(公告)号：US20090170268A1

    公开(公告)日：2009-07-02

    申请号：US11965415

    申请日：2007-12-27

    申请人： Lee Wee Teo ,  Alain Chan ,  Chung Foong Tan ,  Elgin Kiok Boone Quek

    发明人： Lee Wee Teo ,  Alain Chan ,  Chung Foong Tan ,  Elgin Kiok Boone Quek

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L29/6653 ,  H01L29/66636

    摘要： A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers adjacent the gate electrode. The epitaxial regions are formed by depositing an epitaxial material into cavities selectively etched into the semiconductor substrate on either side of the gate electrode. The masking sidewall spacers limit the thickness of the epitaxial deposited material in proximity of the gate electrode, such that the upper surface of the epitaxial material is substantially the same as the principal surface of the semiconductor substrate. Doped regions are formed in the channel region beneath the gate electrode using an angled ion beam, such that doping profiles of the implanted regions are substantially unaffected by surface irregularities in the epitaxially-deposited material.

    摘要翻译： 用于制造诸如应变通道晶体管的半导体器件的工艺包括在靠近栅电极的衬底中形成外延区域，其中通过掩蔽邻近栅电极的侧壁间隔来限定外延区域的表面轮廓。 通过将外延材料沉积到选择性地蚀刻到栅电极的任一侧上的半导体衬底中的空腔中形成外延区域。 掩蔽侧壁间隔物限制了栅极附近的外延沉积材料的厚度，使得外延材料的上表面与半导体衬底的主表面基本上相同。 使用成角度的离子束在栅电极下方的沟道区域中形成掺杂区域，使得注入区域的掺杂分布基本上不受外延沉积材料中的表面不规则性的影响。

    Process for fabricating a semiconductor device having embedded epitaxial regions
    4.
    发明授权
    Process for fabricating a semiconductor device having embedded epitaxial regions 有权
    具有嵌入式外延区域的半导体器件的制造方法

    公开(公告)号：US07994010B2

    公开(公告)日：2011-08-09

    申请号：US11965415

    申请日：2007-12-27

    申请人： Lee Wee Teo ,  Alain Chan ,  Chung Foong Tan ,  Elgin Kiok Boone Quek

    发明人： Lee Wee Teo ,  Alain Chan ,  Chung Foong Tan ,  Elgin Kiok Boone Quek

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L29/6653 ,  H01L29/66636

    摘要： A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers adjacent the gate electrode. The epitaxial regions are formed by depositing an epitaxial material into cavities selectively etched into the semiconductor substrate on either side of the gate electrode. The masking sidewall spacers limit the thickness of the epitaxial deposited material in proximity of the gate electrode, such that the upper surface of the epitaxial material is substantially the same as the principal surface of the semiconductor substrate. Doped regions are formed in the channel region beneath the gate electrode using an angled ion beam, such that doping profiles of the implanted regions are substantially unaffected by surface irregularities in the epitaxially-deposited material.

    摘要翻译： 用于制造诸如应变通道晶体管的半导体器件的工艺包括在靠近栅电极的衬底中形成外延区域，其中通过掩蔽邻近栅电极的侧壁间隔来限定外延区域的表面轮廓。 通过将外延材料沉积到选择性地蚀刻到栅电极的任一侧上的半导体衬底中的空腔中形成外延区域。 掩蔽侧壁间隔物限制了栅极附近的外延沉积材料的厚度，使得外延材料的上表面与半导体衬底的主表面基本上相同。 使用成角度的离子束在栅电极下方的沟道区域中形成掺杂区域，使得注入区域的掺杂分布基本上不受外延沉积材料中的表面不规则性的影响。