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    AD-HOC NETWORK ROUTING METRIC OPTIMIZATION
    2.
    发明申请
    AD-HOC NETWORK ROUTING METRIC OPTIMIZATION 有权
    AD-HOC网络路由计量优化

    公开(公告)号：US20070140129A1

    公开(公告)日：2007-06-21

    申请号：US11612847

    申请日：2006-12-19

    申请人： Fred Bauer ,  Peter Cnudde ,  Lee Yang

    发明人： Fred Bauer ,  Peter Cnudde ,  Lee Yang

    IPC分类号： H04J3/14

    CPC分类号： H04W40/04 ,  H04L45/124 ,  H04W40/14 ,  H04W84/18 ,  Y02D70/142 ,  Y02D70/22 ,  Y02D70/32 ,  Y02D70/34

    摘要： A network processing device calculates variable link metrics and then prioritizes selection of network links for sending packets according to the calculated variable link metrics. The variable link metrics can include a link capacity index that represents a combination of platform and interface capabilities for nodes on opposite ends of the network links. The link metrics can also include an expected retransmission value that indicates the percentage of packets that may have to be transmitted over different links.

    摘要翻译： 网络处理设备计算可变链路度量，然后根据计算的可变链路度量优先选择用于发送分组的网络链路。 可变链路度量可以包括代表网络链路的相对端上的节点的平台和接口能力的组合的链路容量索引。 链路度量还可以包括指示可能必须通过不同链路传输的分组的百分比的预期重传值。

    Ad-hoc network routing metric optimization
    3.
    发明授权
    Ad-hoc network routing metric optimization 有权
    自组织网络路由度量优化

    公开(公告)号：US07710896B2

    公开(公告)日：2010-05-04

    申请号：US11612847

    申请日：2006-12-19

    申请人： Fred Bauer ,  Peter Cnudde ,  Lee Yang

    发明人： Fred Bauer ,  Peter Cnudde ,  Lee Yang

    IPC分类号： H04L1/00

    CPC分类号： H04W40/04 ,  H04L45/124 ,  H04W40/14 ,  H04W84/18 ,  Y02D70/142 ,  Y02D70/22 ,  Y02D70/32 ,  Y02D70/34

    摘要： A network processing device calculates variable link metrics and then prioritizes selection of network links for sending packets according to the calculated variable link metrics. The variable link metrics can include a link capacity index that represents a combination of platform and interface capabilities for nodes on opposite ends of the network links. The link metrics can also include an expected retransmission value that indicates the percentage of packets that may have to be transmitted over different links.

    摘要翻译： 网络处理设备计算可变链路度量，然后根据计算的可变链路度量优先选择用于发送分组的网络链路。 可变链路度量可以包括代表网络链路的相对端上的节点的平台和接口能力的组合的链路容量索引。 链路度量还可以包括指示可能必须通过不同链路传输的分组的百分比的预期重传值。

    All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages
    4.
    发明授权
    All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages 失效
    全CMOS高阻抗输出缓冲器，用于由多个电源电压驱动的总线

    公开(公告)号：US5444397A

    公开(公告)日：1995-08-22

    申请号：US318238

    申请日：1994-10-05

    申请人： Anthony Y. Wong ,  David Kwong ,  Lee Yang ,  Charles Hsiao

    发明人： Anthony Y. Wong ,  David Kwong ,  Lee Yang ,  Charles Hsiao

    IPC分类号： H03K19/00 ,  H01L27/02 ,  H01L27/118 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/02

    CPC分类号： H03K19/00315 ,  H01L27/0218 ,  H01L27/11898 ,  H03K2217/0018

    摘要： An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.

    摘要翻译： 全CMOS输出缓冲器驱动可在3伏和5伏电压下工作的总线。 当处于高阻抗状态时，输出缓冲器很少或没有电流。 如果总线通过外部设备驱动到5伏特，则高阻抗输出缓冲器可能会因总线逻辑电平而产生闩锁和失真，因为它只有3伏电源，不使用电荷泵或 额外的5伏电源。 偏置电路将包含p沟道晶体管的N阱和驱动晶体管耦合到被驱动到5伏特的总线。 因此，N阱也被驱动到5伏，即总线上的电压。 高阻抗输出缓冲器中的p沟道驱动晶体管的栅极也通过另一个p沟道晶体管耦合到N阱，将栅极电位提高到5伏。 因此，p沟道驱动晶体管的栅极和体是5伏特，消除了反向电流和闭锁问题。 传输门将p沟道驱动晶体管的栅极与器件电路的其余部分隔离。 传输门，偏置电路和驱动晶体管的p沟道晶体管位于N阱中，仅在必要时才被偏置到5伏特。 因此，在正常工作期间，驱动晶体管的N阱处于3伏特，消除了体内效应的性能损失。 逻辑门增加了阱偏压，只有当必要时才能将驱动器门隔离，当总线为高电平并由5伏器件驱动时，输出缓冲器处于高阻态。