公开(公告)号：US20050236687A1

公开(公告)日：2005-10-27

申请号：US10830347

申请日：2004-04-22

申请人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

发明人： Kevin Chan ,  Bruce Doris ,  Kathryn Guarini ,  Meikei Ieong ,  Shreesh Narasimha ,  Alexander Reznicek ,  Kern Rim ,  Devendra Sadana ,  Leathen Shi ,  Jeffrey Sleight ,  Min Yang

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

摘要翻译： 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US20060275961A1

公开(公告)日：2006-12-07

申请号：US11492271

申请日：2006-07-25

申请人： Kevin Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra Sadana ,  Leathen Shi ,  Min Yang

发明人： Kevin Chan ,  Meikei Ieong ,  Alexander Reznicek ,  Devendra Sadana ,  Leathen Shi ,  Min Yang

IPC分类号： H01L21/84

CPC分类号： H01L29/7842 ,  H01L21/2022 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/78687

摘要： Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.

摘要翻译： 提供了形成应变含Si的杂化基板的方法以及通过这些方法形成的应变的含Si杂化基板。 在本发明的方法中，形成覆盖重新生长的半导体材料，第二半导体层或两者的应变Si层。 根据本发明，应变Si层具有与再生长半导体层或第二半导电层相同的晶体取向。 该方法提供混合基板，其中至少一个器件层包括应变Si。

公开(公告)号：US20050285159A1

公开(公告)日：2005-12-29

申请号：US10875727

申请日：2004-06-24

申请人： Kevin Chan ,  Kathryn Guarini ,  Meikel Ieong ,  Kern Rim ,  Min Yang

发明人： Kevin Chan ,  Kathryn Guarini ,  Meikel Ieong ,  Kern Rim ,  Min Yang

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/045 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/823807 ,  H01L29/1054

摘要： A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600° C. and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HCl acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.

摘要翻译： 描述了用于导电载体的结构和形成方法，其结合了具有在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此形成PS形态层 正在紧张。 描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃来形成拟态或外延层的步骤，并引入含Si气体 和含Ge的气体。 描述了一种用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCl酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底 以获得不含杂质且RMS小于0.1nm的衬底表面。

公开(公告)号：US20060194414A1

公开(公告)日：2006-08-31

申请号：US11411395

申请日：2006-04-26

申请人： Kevin Chan ,  Kathryn Guarini ,  Erin Jones ,  Antonio Saavedra ,  Leathen Shi ,  Dinkar Singh

发明人： Kevin Chan ,  Kathryn Guarini ,  Erin Jones ,  Antonio Saavedra ,  Leathen Shi ,  Dinkar Singh

IPC分类号： H01L21/30

CPC分类号： H01L21/02052 ,  H01L21/02164 ,  H01L21/02343 ,  H01L21/2007 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/31612 ,  H01L21/31662 ,  H01L21/76251

摘要： Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.

摘要翻译： 描述了涉及NH 4 OH的湿化学表面处理，其能够使诸如半导体（例如Si）的两个晶片与绝缘体（例如，SiO 2）的极强直接接合， 在低温（小于或等于400℃）。 使用这些表面处理中的一些已经实现了键合界面的高达〜4835±675mJ / m 2的表面能。 该值与显着更高的处理温度（小于1000℃）报告的值相当。 本文还可以实现具有优异产率和约2500mJ / m 2的表面能的无空隙键合界面。

公开(公告)号：US20070155130A1

公开(公告)日：2007-07-05

申请号：US11684855

申请日：2007-03-12

申请人： Kevin Chan ,  Jack Chan ,  Kern Rim ,  Leathen Shi

发明人： Kevin Chan ,  Jack Chan ,  Kern Rim ,  Leathen Shi

IPC分类号： H01L21/302

CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

公开(公告)号：US20060001088A1

公开(公告)日：2006-01-05

申请号：US10883443

申请日：2004-07-01

申请人： Kevin Chan ,  Jack Chu ,  Kern Rim ,  Leathen Shi

发明人： Kevin Chan ,  Jack Chu ,  Kern Rim ,  Leathen Shi

IPC分类号： H01L21/00 ,  H01L31/0392

CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate comprising a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer. Specifically, the method includes forming a first multilayered structure comprising at least a tensile-strained SiGe alloy layer located above a relaxed SiGe alloy layer, wherein the tensile-strained SiGe alloy contains a lower Ge content than the relaxed SiGe alloy layer; bonding the first multilayered structure to an insulating layer of a second multilayered structure on a surface opposite the relaxed SiGe alloy layer; and removing the relaxed SiGe alloy layer.

摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。 具体地说，该方法包括形成至少包含位于松弛SiGe合金层上方的拉伸应变SiGe合金层的第一多层结构，其中拉伸应变SiGe合金含有比松弛SiGe合金层低的Ge含量; 将第一多层结构结合到与松弛SiGe合金层相对的表面上的第二多层结构的绝缘层; 并去除松弛的SiGe合金层。

公开(公告)号：US20060024931A1

公开(公告)日：2006-02-02

申请号：US10902557

申请日：2004-07-29

申请人： Kevin Chan ,  Joel de Souza ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger

发明人： Kevin Chan ,  Joel de Souza ,  Alexander Reznicek ,  Devendra Sadana ,  Katherine Saenger

IPC分类号： H01L21/20 ,  H01L21/425 ,  H01L21/762 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/1203 ,  H01L27/1207

摘要： This invention provides a separation by implanted oxygen (SIMOX) method for forming planar hybrid orientation semiconductor-on-insulator (SOI) substrates having different crystal orientations, thereby making it possible for devices to be fabricated on crystal orientations providing optimal performance. The method includes the steps of selecting a substrate having a base semiconductor layer having a first crystallographic orientation separated by a thin insulating layer from a top semiconductor layer having a second crystallographic orientation; replacing the top semiconductor layer in selected regions with an epitaxially grown semiconductor having the first crystallographic orientation; then using an ion implantation and annealing method to (i) form a buried insulating region within the epitaxially grown semiconductor material, and (ii) thicken the insulating layer underlying the top semiconductor layer, thereby forming a hybrid orientation substrate in which the two semiconductor materials with different crystallographic orientations have substantially the same thickness and are both disposed on a common buried insulator layer. In a variation of this method, an ion implantation and annealing method is instead used to extend an auxiliary buried insulator layer (initially underlying the base semiconductor layer) upwards (i) into the epitaxially grown semiconductor, and (ii) up to the insulating layer underlying the top semiconductor layer.

摘要翻译： 本发明提供了通过注入氧（SIMOX）分离方法，用于形成具有不同晶体取向的平面杂化取向绝缘体上半导体（SOI）衬底，从而使得可以以提供最佳性能的晶体取向来制造器件。 该方法包括以下步骤：从具有第二晶体取向的顶部半导体层选择具有由薄绝缘层分离的第一晶体取向的基底半导体层的衬底; 用具有第一晶体取向的外延生长的半导体代替选定区域中的顶部半导体层; 然后使用离子注入和退火方法来（i）在外延生长的半导体材料内形成掩埋绝缘区，并且（ii）加厚顶部半导体层下面的绝缘层，从而形成混合取向基板，其中两个半导体材料 具有不同的晶体取向具有基本上相同的厚度并且均设置在公共掩埋绝缘体层上。 在该方法的变型中，替代地使用离子注入和退火方法将辅助掩埋绝缘体层（最初在基底半导体层下面）向上（i）延伸到外延生长的半导体中，以及（ii）直到绝缘层 在顶部半导体层下面。

公开(公告)号：US20080042166A1

公开(公告)日：2008-02-21

申请号：US11927006

申请日：2007-10-29

申请人： Kevin Chan ,  Jack Chu ,  Kern Rim ,  Leathen Shi

发明人： Kevin Chan ,  Jack Chu ,  Kern Rim ,  Leathen Shi

IPC分类号： H01L29/06

CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

公开(公告)号：US20050263797A1

公开(公告)日：2005-12-01

申请号：US11146624

申请日：2005-06-07

申请人： Kevin Chan ,  Guy Cohen ,  Meikei Ieong ,  Ronnen Roy ,  Paul Solomon ,  Min Yang

发明人： Kevin Chan ,  Guy Cohen ,  Meikei Ieong ,  Ronnen Roy ,  Paul Solomon ,  Min Yang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/148 ,  H01L29/76 ,  H01L29/768 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66484 ,  H01L21/26533 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7831 ,  H01L29/7834 ,  H01L29/78648

摘要： A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

摘要翻译： 提供了双栅场效应晶体管（DGFET）结构和形成这样的结构的方法，其中源/漏区下的寄生电容大大减小。 提供了两种降低源极/漏极区下寄生电容的新手段。 首先，栅极外部的硅区域被转换为氧化物，同时用第一间隔物保护邻近栅极的硅凸缘。 使用自对准氧植入物或某些其它物种的植入物可以促进氧化。 其次，去除第一间隔物，用第二间隔物代替，通过采用横向选择性外延生长并使用现在暴露的硅壁缘作为种子，在自对准氧化物隔离区域上生长新的硅源/漏区。 这实现了对背板的低电容，同时保持阈值电压的控制。

公开(公告)号：US20070278517A1

公开(公告)日：2007-12-06

申请号：US11840029

申请日：2007-08-16

申请人： Diane Boyd ,  Juan Cai ,  Kevin Chan ,  Patricia Mooney ,  Kern Rim

发明人： Diane Boyd ,  Juan Cai ,  Kevin Chan ,  Patricia Mooney ,  Kern Rim

IPC分类号： H01L35/26 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/7842 ,  Y10S438/938

摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

摘要翻译： 本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。 以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。 通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。 然后在含有受损区域的含Si衬底上形成应变SiGe合金。 然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。 接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。