System for providing universal cross-connect connectivity in a central office
    2.
    发明授权
    System for providing universal cross-connect connectivity in a central office 失效
    用于在中心局提供通用交叉连接的系统

    公开(公告)号:US06766022B1

    公开(公告)日:2004-07-20

    申请号:US09664243

    申请日:2000-09-18

    IPC分类号: H04M900

    摘要: A system for cross-connecting network elements of different types through a common universal media. In the system, a media conversion interface is electrically connected to a network element. This media conversion interface passively maps the connector and cable type of the network element to a universal connector type. This media conversion interface is electrically connected to a cross-connect module in a universal distribution frame. This electrical connection uses a universal cable group and universal connectors. This cross-connect module is connected to another cross-connect module, also in a universal distribution frame, using a universal cable group and universal connectors. This second cross-connect module is electrically connected to a second media conversion interface, using a universal cable group and universal connectors. This second media conversion interface is electrically connected to a second network element, and passively maps the connector and cable type of the second network element to the universal connector.

    摘要翻译: 通过普通通用介质交换不同类型网络元件的系统。 在该系统中,媒体转换接口电连接到网络元件。 该媒体转换接口被动地将网络元件的连接器和电缆类型映射到通用连接器类型。 该媒体转换接口电连接到通用配线架中的交叉连接模块。 该电气连接使用通用电缆组和通用连接器。 该交叉连接模块使用通用电缆组和通用连接器连接到另一个交叉连接模块,也在通用配线架中。 该第二交叉连接模块使用通用电缆组和通用连接器电连接到第二介质转换接口。 该第二媒体转换接口电连接到第二网络元件,并且被动地将第二网络元件的连接器和电缆类型映射到通用连接器。

    Distributed digital conferencing system
    4.
    发明授权
    Distributed digital conferencing system 失效
    分布式数字会议系统

    公开(公告)号:US4389720A

    公开(公告)日:1983-06-21

    申请号:US256937

    申请日:1981-04-23

    IPC分类号: H04M3/56 H04Q11/04

    CPC分类号: H04Q11/0407 H04M3/561

    摘要: In time division communication systems one conference technique is to have a processor combine those samples going to a particular station forming a conference having as many subcombinations as there are stations. This approach, while allowing individual station gain adjustment, suffers from its dependence upon a large number of logic operations for a given conference. A modification of this technique is disclosed which uses a distributed structure such that the individual station ports, under local memory and processor control, operate to combine selected time slot samples into a conference sum unique to the station. In this manner gain values may be assigned on an individual listener station basis while the logic processing for the conference is performed in parallel by the ports involved in the conference.

    摘要翻译: 在时分通信系统中,一种会议技术是使处理器将到达特定站的样本组合成具有与站有多个子组合的会议。 这种方法在允许单独的站增益调整的同时,受到对给定会议的大量逻辑运算的依赖。 公开了该技术的修改,其使用分布式结构,使得在本地存储器和处理器控制下的各个站端口操作以将所选择的时隙样本组合成该站所特有的会议总和。 以这种方式,可以在单个侦听站基础上分配增益值,同时会议的逻辑处理由会议中涉及的端口并行执行。

    Digital loop synchronization circuit
    5.
    发明授权
    Digital loop synchronization circuit 失效
    数字环路同步电路

    公开(公告)号:US4306304A

    公开(公告)日:1981-12-15

    申请号:US062425

    申请日:1979-07-31

    摘要: There is disclosed a digital loop circuit for controlling synchronization around a closed loop communication system. The control circuit is designed to automatically adjust the delay of the loop to maintain a constant frame bit length without regard to the number of stations connected into the loop. As stations are added or subtracted from the loop, the system operates to add or subtract delay as necessary. A FIFO register having a bit capacity equal to the frame size is inserted serially in the loop and a separate clock is used to control the input and the output of the FIFO register. If a unique frame bit is not received in the anticipated position the output FIFO clock skips one count per frame thereby adding delay to the loop. The loop control circuit operates for situations where the framing bit is on a separate channel and also when the framing bit is on the actual data channel.

    摘要翻译: 公开了一种用于控制围绕闭环通信系统的同步的数字环路电路。 控制电路被设计为自动调整回路的延迟以保持恒定的帧位长度,而不考虑连接到回路中的站数。 由于从循环中添加或减少站,系统将根据需要进行加法或减法延迟。 具有等于​​帧大小的位容量的FIFO寄存器被串行地插入到环路中,并且使用单独的时钟来控制FIFO寄存器的输入和输出。 如果在预期位置没有接收到唯一的帧位,则输出FIFO时钟跳过每帧一个计数,从而将延迟添加到循环。 环路控制电路适用于成帧位在单独信道上的情况,并且当成帧位在实际数据信道上时。

    Variable time slot communication system
    6.
    发明授权
    Variable time slot communication system 失效
    可变时隙通信系统

    公开(公告)号:US4809270A

    公开(公告)日:1989-02-28

    申请号:US150489

    申请日:1988-02-11

    IPC分类号: H04J3/16 H04M3/56 H04Q11/04

    摘要: A time division communication system having peripheral devices controlled om a port circuit is arranged such that the port circuit may have assigned to it a variable number of time slots for any peripheral device associated therewith. Each port circuit has a microprocessor control device which is capable of controlling communication to or from the port circuit over the system time division bus or to and from the port circuit and the peripheral over a variable number of time slots, none of which are preassigned to the port circuit.

    摘要翻译: 具有从端口电路控制的外围设备的时分通信系统被布置成使得端口电路可以向其分配用于与其相关联的任何外围设备的可变数量的时隙。 每个端口电路都具有一个微处理器控制装置,其能够通过系统时分总线或通过可变数量的时隙来控制与端口电路的通信,或者可以在端口电路和外围设备上进行通信,而这些时隙不被预先分配给 端口电路。

    Dual bus communication system
    7.
    发明授权
    Dual bus communication system 失效
    双总线通信系统

    公开(公告)号:US4535448A

    公开(公告)日:1985-08-13

    申请号:US448771

    申请日:1982-12-10

    CPC分类号: H04L12/64 H04L12/28

    摘要: A dual set of busses is used to provide close coupling between the data and voice services of the CS300 communication system. One of these busses is a time division multiplex bus arranged for communication between port access circuits, and the other bus is a packet-switched data processing bus used for interfacing both with the system peripherals and with the port access circuits. The port access circuits, as well as the faster peripheral circuits, can be connected to either or both busses thereby allowing for the efficient easy interchange of information.

    摘要翻译: 双组合总线用于提供CS300通信系统的数据和语音业务之间的紧密耦合。 这些总线中的一个是布置用于端口访问电路之间的通信的时分复用总线,另一总线是用于与系统外围设备和端口访问电路进行接口的分组交换数据处理总线。 端口访问电路以及更快的外围电路可以连接到一个或两个总线,从而允许有效的信息交换。

    Digital communication system fault isolation circuit
    8.
    发明授权
    Digital communication system fault isolation circuit 失效
    数字通讯系统故障隔离电路

    公开(公告)号:US4279034A

    公开(公告)日:1981-07-14

    申请号:US94494

    申请日:1979-11-15

    申请人: Leslie A. Baxter

    发明人: Leslie A. Baxter

    CPC分类号: H04L12/437 H04B1/745

    摘要: There is disclosed, for use in a digital communication system, a fault detector circuit operable for removing faulty stations from the system. The disclosed circuit uses a distributed bypass isolation technique and may be used with individual stations or with groups of stations. A multi-bit delay register is connected across each station or station group and the output of the delay register is compared with the output of the parallel stations. When differences in the compared bits are detected the parallel stations are immediately isolated from the system and the bits from the delay register are placed in the system to preserve synchronism. This arrangement has the advantage of allowing immediate corrective action to occur to protect the sanity of the system. In situations where the system is divided into a voice digital bus and a data digital bus different error techniques may be employed for each bus.

    摘要翻译: 公开了一种用于数字通信系统中的故障检测器电路,用于从系统中去除故障站。 所公开的电路使用分布式旁路隔离技术,并且可以与各个站或站的组一起使用。 在每个站或站组之间连接多位延迟寄存器,并将延迟寄存器的输出与并行站的输出进行比较。 当检测到比较位的差异时,并行站立即与系统隔离,并且来自延迟寄存器的位被放置在系统中以保持同步。 这种安排具有允许立即采取纠正措施来保护系统的健全性的优点。 在系统分为语音数字总线和数据总线的情况下,每个总线可以采用不同的错误技术。