利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

40 条记录 (耗时 0.031 秒)

    System and Method of Leakage Control in an Asynchronous System
    4.
    发明申请
    System and Method of Leakage Control in an Asynchronous System 有权
    异步系统泄漏控制系统与方法

    公开(公告)号：US20090172452A1

    公开(公告)日：2009-07-02

    申请号：US11964072

    申请日：2007-12-26

    申请人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

    发明人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

    IPC分类号： G06F1/26

    CPC分类号： H03K19/0016 ,  G06F9/3871

    摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

    摘要翻译： 公开了异步管道中泄漏控制的系统和方法。 在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作 阶段。

    Semiconductor device having on-chip voltage regulator
    5.
    发明授权
    Semiconductor device having on-chip voltage regulator 有权
    具有片上稳压器的半导体器件

    公开(公告)号：US08760217B2

    公开(公告)日：2014-06-24

    申请号：US13034845

    申请日：2011-02-25

    申请人： Lew G. Chua-Eoan ,  Charlie Matar ,  Matthew L. Severson ,  Xiaohua Kong

    发明人： Lew G. Chua-Eoan ,  Charlie Matar ,  Matthew L. Severson ,  Xiaohua Kong

    IPC分类号： G11C5/14

    CPC分类号： G06F1/26 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/172

    摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

    摘要翻译： 公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。 半导体器件包括位于接地总线和电源总线之间的电路。 电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。 监视器位于接地总线和电源总线之间。 监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。 控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

    Leakage reduction in electronic circuits
    6.
    发明授权
    Leakage reduction in electronic circuits 有权
    电子线路漏电减少

    公开(公告)号：US07936205B2

    公开(公告)日：2011-05-03

    申请号：US12486159

    申请日：2009-06-17

    申请人： Xiaohua Kong ,  Lew G. Chua-Eoan

    发明人： Xiaohua Kong ,  Lew G. Chua-Eoan

    IPC分类号： H03K3/01

    CPC分类号： H03K19/0013 ,  H03K19/0016

    摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

    摘要翻译： 在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。 电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。 功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。 功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

    System and method of leakage control in an asynchronous system
    7.
    发明授权
    System and method of leakage control in an asynchronous system 有权
    异步系统中的泄漏控制系统和方法

    公开(公告)号：US08527797B2

    公开(公告)日：2013-09-03

    申请号：US11964072

    申请日：2007-12-26

    申请人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

    发明人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

    IPC分类号： G06F1/32

    CPC分类号： H03K19/0016 ,  G06F9/3871

    摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

    摘要翻译： 公开了异步管道中泄漏控制的系统和方法。 在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作 阶段。

    Semiconductor Device Having On-Chip Voltage Regulator
    8.
    发明申请
    Semiconductor Device Having On-Chip Voltage Regulator 有权
    具有片上稳压器的半导体器件

    公开(公告)号：US20120218005A1

    公开(公告)日：2012-08-30

    申请号：US13034845

    申请日：2011-02-25

    申请人： Lew G. Chua-Eoan ,  Charles Matar ,  Matthew L. Severson ,  Xiaohua Kong

    发明人： Lew G. Chua-Eoan ,  Charles Matar ,  Matthew L. Severson ,  Xiaohua Kong

    IPC分类号： G05F1/10 ,  H03B21/00

    CPC分类号： G06F1/26 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/172

    摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

    摘要翻译： 公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。 半导体器件包括位于接地总线和电源总线之间的电路。 电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。 监视器位于接地总线和电源总线之间。 监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。 控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

    Leakage Reduction in Electronic Circuits
    9.
    发明申请
    Leakage Reduction in Electronic Circuits 有权
    电子线路漏电减少

    公开(公告)号：US20100321102A1

    公开(公告)日：2010-12-23

    申请号：US12486159

    申请日：2009-06-17

    申请人： Xiaohua Kong ,  Lew G. Chua-Eoan

    发明人： Xiaohua Kong ,  Lew G. Chua-Eoan

    IPC分类号： G05F1/10

    CPC分类号： H03K19/0013 ,  H03K19/0016

    摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

    摘要翻译： 在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。 电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。 功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。 功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

    Methods and circuits for optimizing performance and power consumption in a design and circuit employing lower threshold voltage (LVT) devices
    10.
    发明授权
    Methods and circuits for optimizing performance and power consumption in a design and circuit employing lower threshold voltage (LVT) devices 有权
    用于在采用较低阈值电压（LVT）器件的设计和电路中优化性能和功耗的方法和电路

    公开(公告)号：US08924902B2

    公开(公告)日：2014-12-30

    申请号：US12683075

    申请日：2010-01-06

    申请人： Lew G. Chua-Eoan

    发明人： Lew G. Chua-Eoan

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5045 ,  G06F17/505 ,  G06F2217/78 ,  G06F2217/84

    摘要： Methods and circuits for optimizing performance and power consumption in a circuit design and circuit employing one or more lower threshold voltage (Lvt) cells or devices are described. A base supply voltage amplitude is determined for providing operating power for the circuit. The base supply voltage amplitude is a low or lowest voltage level that still satisfies a performance specification for the circuit. Providing a low or lowest base supply voltage level reduces or minimizes the standby (i.e., non-switching) power consumption in the Lvt device(s) since current leakage is reduced as the supply voltage level is reduced. Reducing the supply voltage level used to power the Lvt device(s) also reduces active power consumption for the circuit as well. Thus, total power consumption is optimized or reduced while still receiving the benefit of using Lvt devices to optimize or increase performance of a circuit layout and circuit.

    摘要翻译： 描述了在采用一个或多个下阈值电压（Lvt）单元或设备的电路设计和电路中优化性能和功耗的方法和电路。 确定基本电源电压幅度以提供电路的工作功率。 基本电源电压幅度是仍然满足电路性能规格的低或最低电压电平。 提供低或最低基准电压电平降低或最小化Lvt装置中的待机（即非切换）功率消耗，因为随着电源电压电平的降低，电流泄漏减小。 降低用于为Lvt设备供电的电源电压也可以降低电路的有功功耗。 因此，总功耗被优化或降低，同时仍然受益于使用Lvt设备来优化或增加电路布局和电路的性能的益处。