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27 条记录 (耗时 0.026 秒)

    System and Method of Leakage Control in an Asynchronous System
    1.
    发明申请
    System and Method of Leakage Control in an Asynchronous System 有权
    异步系统泄漏控制系统与方法

    公开(公告)号：US20090172452A1

    公开(公告)日：2009-07-02

    申请号：US11964072

    申请日：2007-12-26

    申请人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

    发明人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

    IPC分类号： G06F1/26

    CPC分类号： H03K19/0016 ,  G06F9/3871

    摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

    摘要翻译： 公开了异步管道中泄漏控制的系统和方法。 在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作 阶段。

    System and method of leakage control in an asynchronous system
    2.
    发明授权
    System and method of leakage control in an asynchronous system 有权
    异步系统中的泄漏控制系统和方法

    公开(公告)号：US08527797B2

    公开(公告)日：2013-09-03

    申请号：US11964072

    申请日：2007-12-26

    申请人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

    发明人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

    IPC分类号： G06F1/32

    CPC分类号： H03K19/0016 ,  G06F9/3871

    摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

    摘要翻译： 公开了异步管道中泄漏控制的系统和方法。 在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作 阶段。

    Gate level reconfigurable magnetic logic
    3.
    发明授权
    Gate level reconfigurable magnetic logic 有权
    门级可重构磁逻辑

    公开(公告)号：US08295082B2

    公开(公告)日：2012-10-23

    申请号：US12192386

    申请日：2008-08-15

    申请人： Lew G. Chua-Eoan ,  Xiaochun Zhu ,  Zhi Zhu

    发明人： Lew G. Chua-Eoan ,  Xiaochun Zhu ,  Zhi Zhu

    IPC分类号： G11C11/14 ,  H03K19/177

    CPC分类号： G11C11/16

    摘要： A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.

    摘要翻译： 可再编程门逻辑并行包括多个非易失性可重新配置的基于电阻状态的存储器电路，其中电路可重新配置以实现或改变所选择的门逻辑， 可配置电阻状态的存储器电路各自适于接收逻辑输入信号。 与多个并行非易失性可重配置电阻状态存储电路串联的评估开关被配置为基于存储器电路的编程状态提供输出信号。 传感器被配置为接收输出信号并且基于输出信号和提供给传感器的参考信号来提供逻辑输出信号。 可重构逻辑可以基于使用自旋转矩传递（STT）磁性隧道结（MTJ）磁阻随机存取存储器（MRAM）作为可再编程存储器元件来实现。 逻辑配置在没有电源的情况下保留。

    Integrated voltage regulator method with embedded passive device(s)
    6.
    发明授权
    Integrated voltage regulator method with embedded passive device(s) 有权
    嵌入式无源器件的集成稳压器方法

    公开(公告)号：US08692368B2

    公开(公告)日：2014-04-08

    申请号：US13367932

    申请日：2012-02-07

    申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    IPC分类号： H01L23/34

    CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

    摘要： A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.

    摘要翻译： 堆叠集成电路（IC）装置包括具有有源面的半导体IC和互连结构。 主动面从电压调节器（MEG）接收稳压电压。 将调节电压提供给半导体IC的VREG的有效部分耦合到互连结构。 包装衬底包括一个或多个包括第一组通孔的电感器。 第一组通孔耦合到互连结构并与有源部分配合以提供用于半导体IC的调节电压。 IC还包括耦合到封装基板的印刷电路板（PCB）。 PCB包括耦合到第一组通孔的第二组通孔。 IC还包括PCB上的一个或多个导电路径。 导电路径将第二组通孔的至少两个通孔耦合在一起。

    Integrated Voltage Regulator Method with Embedded Passive Device(s)
    8.
    发明申请
    Integrated Voltage Regulator Method with Embedded Passive Device(s) 有权
    带嵌入式无源器件的集成稳压器方法

    公开(公告)号：US20120293972A1

    公开(公告)日：2012-11-22

    申请号：US13367932

    申请日：2012-02-07

    申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    IPC分类号： H01L23/12 ,  H01L21/50

    CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

    摘要： A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.

    摘要翻译： 堆叠集成电路（IC）装置包括具有有源面的半导体IC和互连结构。 主动面从电压调节器（MEG）接收稳压电压。 将调节电压提供给半导体IC的VREG的有效部分耦合到互连结构。 包装衬底包括一个或多个包括第一组通孔的电感器。 第一组通孔耦合到互连结构并与有源部分配合以提供用于半导体IC的调节电压。 IC还包括耦合到封装衬底的印刷电路板（PCB）。 PCB包括耦合到第一组通孔的第二组通孔。 IC还包括PCB上的一个或多个导电路径。 导电路径将第二组通孔的至少两个通孔耦合在一起。

    Integrated Voltage Regulator with Embedded Passive Device(s)
    9.
    发明申请
    Integrated Voltage Regulator with Embedded Passive Device(s) 审中-公开
    带嵌入式无源器件的集成稳压器

    公开(公告)号：US20110050334A1

    公开(公告)日：2011-03-03

    申请号：US12552321

    申请日：2009-09-02

    申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    IPC分类号： H01L25/00

    CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

    摘要： A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate.

    摘要翻译： 半导体封装系统具有其中部分或完全嵌入电感器和/或电容器的封装衬底。 电压调节器的有源部分安装在封装基板上，并将稳定的电压提供给也安装在封装基板上的管芯。 或者，电压调节器的有源部分集成到管芯中，电压调节器将电压提供给。 电压调节器与电感器和/或电容器配合以向模具提供电压。 电感器可以穿过封装衬底中的通孔。 对于额外的电感，通过安装封装衬底的印刷电路板中的通孔可以耦合到封装衬底中的通孔。

    Gate Level Reconfigurable Magnetic Logic
    10.
    发明申请
    Gate Level Reconfigurable Magnetic Logic 有权
    门级可重构磁逻辑

    公开(公告)号：US20100039136A1

    公开(公告)日：2010-02-18

    申请号：US12192386

    申请日：2008-08-15

    申请人： Lew G. Chua-Eoan ,  Xiaochun Zhu ,  Zhi Zhu

    发明人： Lew G. Chua-Eoan ,  Xiaochun Zhu ,  Zhi Zhu

    IPC分类号： H03K19/173

    CPC分类号： G11C11/16

    摘要： A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.

    摘要翻译： 可再编程门逻辑并行包括多个非易失性可重新配置的基于电阻状态的存储器电路，其中电路可重新配置以实现或改变所选择的门逻辑， 可配置电阻状态的存储器电路各自适于接收逻辑输入信号。 与多个并行非易失性可重配置电阻状态存储电路串联的评估开关被配置为基于存储器电路的编程状态提供输出信号。 传感器被配置为接收输出信号并且基于输出信号和提供给传感器的参考信号来提供逻辑输出信号。 可重构逻辑可以基于使用自旋转矩传递（STT）磁性隧道结（MTJ）磁阻随机存取存储器（MRAM）作为可再编程存储器元件来实现。 逻辑配置在没有电源的情况下保留。