公开(公告)号：US20090172452A1

公开(公告)日：2009-07-02

申请号：US11964072

申请日：2007-12-26

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

IPC分类号： G06F1/26

CPC分类号： H03K19/0016 ,  G06F9/3871

摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

摘要翻译： 公开了异步管道中泄漏控制的系统和方法。 在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作 阶段。

公开(公告)号：US08760217B2

公开(公告)日：2014-06-24

申请号：US13034845

申请日：2011-02-25

申请人： Lew G. Chua-Eoan ,  Charlie Matar ,  Matthew L. Severson ,  Xiaohua Kong

发明人： Lew G. Chua-Eoan ,  Charlie Matar ,  Matthew L. Severson ,  Xiaohua Kong

IPC分类号： G11C5/14

CPC分类号： G06F1/26 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/172

摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

摘要翻译： 公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。 半导体器件包括位于接地总线和电源总线之间的电路。 电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。 监视器位于接地总线和电源总线之间。 监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。 控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

公开(公告)号：US07936205B2

公开(公告)日：2011-05-03

申请号：US12486159

申请日：2009-06-17

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan

IPC分类号： H03K3/01

CPC分类号： H03K19/0013 ,  H03K19/0016

摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

摘要翻译： 在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。 电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。 功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。 功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

公开(公告)号：US08527797B2

公开(公告)日：2013-09-03

申请号：US11964072

申请日：2007-12-26

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

IPC分类号： G06F1/32

CPC分类号： H03K19/0016 ,  G06F9/3871

摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

摘要翻译： 公开了异步管道中泄漏控制的系统和方法。 在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作 阶段。

公开(公告)号：US20110193589A1

公开(公告)日：2011-08-11

申请号：US12703233

申请日：2010-02-10

申请人： Lew G. Chua-Eoan ,  Boris Andreev ,  Christopher Phan ,  Amirali Shayan ,  Xiaohua Kong ,  Mikhail Popovich ,  Mauricio Calle ,  IK-Joon Chang

发明人： Lew G. Chua-Eoan ,  Boris Andreev ,  Christopher Phan ,  Amirali Shayan ,  Xiaohua Kong ,  Mikhail Popovich ,  Mauricio Calle ,  IK-Joon Chang

IPC分类号： H03K19/00 ,  G01R19/00

CPC分类号： G01R31/31721 ,  G01R29/26

摘要： An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

摘要翻译： 片上传感器测量半导体芯片上的动态电源噪声，如电压下降。 采用原位逻辑，对芯片功能逻辑电源上存在的噪声敏感。 示例性功能逻辑包括芯片的微处理器，加法器和/或其他功能逻辑。 原位逻辑执行一些操作，并且执行该操作所需的时间量（即，操作延迟）对电源上存在的噪声敏感。 因此，通过评估原位逻辑的操作延迟，可以测量电源上存在的噪声量。

公开(公告)号：US20120218005A1

公开(公告)日：2012-08-30

申请号：US13034845

申请日：2011-02-25

申请人： Lew G. Chua-Eoan ,  Charles Matar ,  Matthew L. Severson ,  Xiaohua Kong

发明人： Lew G. Chua-Eoan ,  Charles Matar ,  Matthew L. Severson ,  Xiaohua Kong

IPC分类号： G05F1/10 ,  H03B21/00

CPC分类号： G06F1/26 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/172

摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

摘要翻译： 公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。 半导体器件包括位于接地总线和电源总线之间的电路。 电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。 监视器位于接地总线和电源总线之间。 监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。 控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

公开(公告)号：US20100321102A1

公开(公告)日：2010-12-23

申请号：US12486159

申请日：2009-06-17

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan

IPC分类号： G05F1/10

CPC分类号： H03K19/0013 ,  H03K19/0016

摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

摘要翻译： 在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。 电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。 功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。 功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

公开(公告)号：US08924902B2

公开(公告)日：2014-12-30

申请号：US12683075

申请日：2010-01-06

申请人： Lew G. Chua-Eoan

发明人： Lew G. Chua-Eoan

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045 ,  G06F17/505 ,  G06F2217/78 ,  G06F2217/84

摘要： Methods and circuits for optimizing performance and power consumption in a circuit design and circuit employing one or more lower threshold voltage (Lvt) cells or devices are described. A base supply voltage amplitude is determined for providing operating power for the circuit. The base supply voltage amplitude is a low or lowest voltage level that still satisfies a performance specification for the circuit. Providing a low or lowest base supply voltage level reduces or minimizes the standby (i.e., non-switching) power consumption in the Lvt device(s) since current leakage is reduced as the supply voltage level is reduced. Reducing the supply voltage level used to power the Lvt device(s) also reduces active power consumption for the circuit as well. Thus, total power consumption is optimized or reduced while still receiving the benefit of using Lvt devices to optimize or increase performance of a circuit layout and circuit.

摘要翻译： 描述了在采用一个或多个下阈值电压（Lvt）单元或设备的电路设计和电路中优化性能和功耗的方法和电路。 确定基本电源电压幅度以提供电路的工作功率。 基本电源电压幅度是仍然满足电路性能规格的低或最低电压电平。 提供低或最低基准电压电平降低或最小化Lvt装置中的待机（即非切换）功率消耗，因为随着电源电压电平的降低，电流泄漏减小。 降低用于为Lvt设备供电的电源电压也可以降低电路的有功功耗。 因此，总功耗被优化或降低，同时仍然受益于使用Lvt设备来优化或增加电路布局和电路的性能的益处。

公开(公告)号：US20120056680A1

公开(公告)日：2012-03-08

申请号：US13294351

申请日：2011-11-11

申请人： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

发明人： Jonghae Kim ,  Shiqun Gu ,  Brian Matthew Henderson ,  Thomas R. Toms ,  Lew G. Chua-Eoan ,  Seyfollah S. Bazarjani ,  Matthew Nowak

IPC分类号： H03F3/16

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01F19/04 ,  H01F2017/002 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2924/3011

摘要： A three dimensional on-chip radio frequency amplifier is disclosed that includes first and second transformers and a first transistor. The first transformer includes first and second inductively coupled inductors. The second transformer includes third and fourth inductively coupled inductors. Each inductor includes multiple first segments in a first metal layer; multiple second segments in a second metal layer; first and second inputs, and multiple through vias coupling the first and second segments to form a continuous path between the first and second inputs. The first input of the first inductor is coupled to an amplifier input; the first input of the second inductor is coupled to the first transistor gate; the first input of the third inductor is coupled to the first transistor drain, the first input of the fourth inductor is coupled to an amplifier output. The second inductor inputs and the first transistor source are coupled to ground.

摘要翻译： 公开了一种三维片上射频放大器，其包括第一和第二变压器和第一晶体管。 第一变压器包括第一和第二电感耦合电感器。 第二变压器包括第三和第四电感耦合电感器。 每个电感器包括在第一金属层中的多个第一段; 第二金属层中的多个第二段; 第一和第二输入以及耦合第一和第二段的多通孔，以形成第一和第二输入之间的连续路径。 第一电感器的第一输入耦合到放大器输入端; 第二电感器的第一输入耦合到第一晶体管栅极; 第三电感器的第一输入耦合到第一晶体管漏极，第四电感器的第一输入耦合到放大器输出端。 第二电感器输入和第一晶体管源耦合到地。

公开(公告)号：US20110234300A1

公开(公告)日：2011-09-29

申请号：US12731455

申请日：2010-03-25

申请人： Junmou Zhang ,  Lew G. Chua-Eoan

发明人： Junmou Zhang ,  Lew G. Chua-Eoan

IPC分类号： G01K7/01

CPC分类号： G01K7/01 ,  G01K2215/00 ,  G05F3/30

摘要： A bandgap sensor which measures temperatures within an integrated circuit is presented. The sensor may include a first transistor having an emitter node coupled in series to a first resistor and a first current source, wherein a PTAT current flows through the first resistor, and a second transistor having a base node coupled to a base node of the first transistor, and a collector node coupled to a collector node of the first transistor, further wherein the first and second transistors are diode connected. The sensor may further include a first operational amplifier providing negative feedback to the first current source, wherein the negative feedback is related to a difference in the base-emitter voltages of the first and second transistors, and a second operational amplifier which couples the base-emitter voltage of the second transistor across a second resistor, wherein a CTAT current flows through the second resistor.

摘要翻译： 提出了一种测量集成电路内温度的带隙传感器。 传感器可以包括具有与第一电阻器和第一电流源串联耦合的发射极节点的第一晶体管，其中PTAT电流流过第一电阻器，以及第二晶体管，具有耦合到第一电阻器的基极节点的基极节点 晶体管和耦合到第一晶体管的集电极节点的集电极节点，其中第一和第二晶体管是二极管连接的。 传感器还可以包括向第一电流源提供负反馈的第一运算放大器，其中所述负反馈与所述第一和第二晶体管的基极 - 发射极电压的差异相关;以及第二运算放大器， 跨越第二电阻器的第二晶体管的发射极电压，其中CTAT电流流过第二电阻器。