公开(公告)号：US20110193589A1

公开(公告)日：2011-08-11

申请号：US12703233

申请日：2010-02-10

申请人： Lew G. Chua-Eoan ,  Boris Andreev ,  Christopher Phan ,  Amirali Shayan ,  Xiaohua Kong ,  Mikhail Popovich ,  Mauricio Calle ,  IK-Joon Chang

发明人： Lew G. Chua-Eoan ,  Boris Andreev ,  Christopher Phan ,  Amirali Shayan ,  Xiaohua Kong ,  Mikhail Popovich ,  Mauricio Calle ,  IK-Joon Chang

IPC分类号： H03K19/00 ,  G01R19/00

CPC分类号： G01R31/31721 ,  G01R29/26

摘要： An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

摘要翻译： 片上传感器测量半导体芯片上的动态电源噪声，如电压下降。 采用原位逻辑，对芯片功能逻辑电源上存在的噪声敏感。 示例性功能逻辑包括芯片的微处理器，加法器和/或其他功能逻辑。 原位逻辑执行一些操作，并且执行该操作所需的时间量（即，操作延迟）对电源上存在的噪声敏感。 因此，通过评估原位逻辑的操作延迟，可以测量电源上存在的噪声量。

公开(公告)号：US08497694B2

公开(公告)日：2013-07-30

申请号：US12703233

申请日：2010-02-10

申请人： Lew Chua-Eoan ,  Boris Andreev ,  Christopher Phan ,  Amirali Shayan ,  Xiaohua Kong ,  Mikhail Popovich ,  Mauricio Calle ,  IK-Joon Chang

发明人： Lew Chua-Eoan ,  Boris Andreev ,  Christopher Phan ,  Amirali Shayan ,  Xiaohua Kong ,  Mikhail Popovich ,  Mauricio Calle ,  IK-Joon Chang

IPC分类号： G01R31/36 ,  G01R31/3187

CPC分类号： G01R31/31721 ,  G01R29/26

摘要： An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

摘要翻译： 片上传感器测量半导体芯片上的动态电源噪声，如电压下降。 采用原位逻辑，对芯片功能逻辑电源上存在的噪声敏感。 示例性功能逻辑包括芯片的微处理器，加法器和/或其他功能逻辑。 原位逻辑执行一些操作，并且执行该操作所需的时间量（即，操作延迟）对电源上存在的噪声敏感。 因此，通过评估原位逻辑的操作延迟，可以测量电源上存在的噪声量。

公开(公告)号：US20090172452A1

公开(公告)日：2009-07-02

申请号：US11964072

申请日：2007-12-26

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

IPC分类号： G06F1/26

CPC分类号： H03K19/0016 ,  G06F9/3871

摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

摘要翻译： 公开了异步管道中泄漏控制的系统和方法。 在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作 阶段。

公开(公告)号：US20120218005A1

公开(公告)日：2012-08-30

申请号：US13034845

申请日：2011-02-25

申请人： Lew G. Chua-Eoan ,  Charles Matar ,  Matthew L. Severson ,  Xiaohua Kong

发明人： Lew G. Chua-Eoan ,  Charles Matar ,  Matthew L. Severson ,  Xiaohua Kong

IPC分类号： G05F1/10 ,  H03B21/00

CPC分类号： G06F1/26 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/172

摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

摘要翻译： 公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。 半导体器件包括位于接地总线和电源总线之间的电路。 电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。 监视器位于接地总线和电源总线之间。 监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。 控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

公开(公告)号：US20100321102A1

公开(公告)日：2010-12-23

申请号：US12486159

申请日：2009-06-17

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan

IPC分类号： G05F1/10

CPC分类号： H03K19/0013 ,  H03K19/0016

摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

摘要翻译： 在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。 电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。 功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。 功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

公开(公告)号：US08527797B2

公开(公告)日：2013-09-03

申请号：US11964072

申请日：2007-12-26

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan ,  Sei Seung Yoon ,  Zhi Zhu

IPC分类号： G06F1/32

CPC分类号： H03K19/0016 ,  G06F9/3871

摘要： Systems and methods of leakage control in an asynchronous pipeline are disclosed. In an embodiment, a signal is received from a preceding stage at an operative stage of an asynchronous circuit device, and a switch associated with the operative stage is activated in response to the control signal being sent to the operative stage to enable power to the operative stage.

摘要翻译： 公开了异步管道中泄漏控制的系统和方法。 在一个实施例中，在异步电路设备的操作阶段从前一级接收信号，并且响应于控制信号被发送到操作级而使与操作级相关联的开关被激活以使能到操作 阶段。

公开(公告)号：US08760217B2

公开(公告)日：2014-06-24

申请号：US13034845

申请日：2011-02-25

申请人： Lew G. Chua-Eoan ,  Charlie Matar ,  Matthew L. Severson ,  Xiaohua Kong

发明人： Lew G. Chua-Eoan ,  Charlie Matar ,  Matthew L. Severson ,  Xiaohua Kong

IPC分类号： G11C5/14

CPC分类号： G06F1/26 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/172

摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

摘要翻译： 公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。 半导体器件包括位于接地总线和电源总线之间的电路。 电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。 监视器位于接地总线和电源总线之间。 监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。 控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

公开(公告)号：US07936205B2

公开(公告)日：2011-05-03

申请号：US12486159

申请日：2009-06-17

申请人： Xiaohua Kong ,  Lew G. Chua-Eoan

发明人： Xiaohua Kong ,  Lew G. Chua-Eoan

IPC分类号： H03K3/01

CPC分类号： H03K19/0013 ,  H03K19/0016

摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

摘要翻译： 在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。 电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。 功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。 功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

公开(公告)号：US09753479B2

公开(公告)日：2017-09-05

申请号：US13564150

申请日：2012-08-01

申请人： Madjid Hafizi ,  Jie Xu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Madjid Hafizi ,  Jie Xu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： G05F3/08 ,  H04L25/02

CPC分类号： G05F3/08 ,  H03F2200/03 ,  H04L25/0278 ,  H04L25/028

摘要： A pre-driver circuit generates a driver bias signal based on a swing command, a driver impedance characteristic, and an input signal. A driver receives the driver bias signal and generates, in response, a driver signal having a swing and having an output impedance corresponding to the bias signal. Optionally, the driver receives power from a switchable one of multiple supply rails, according to the swing. Optionally, the driver has voltage controlled resistor elements and the driver bias signal is generated based on the swing command and a replica of the driver voltage controlled resistor elements.

公开(公告)号：US08630821B2

公开(公告)日：2014-01-14

申请号：US13189926

申请日：2011-07-25

申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

IPC分类号： G06F11/30

CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。