公开(公告)号：US20240339572A1

公开(公告)日：2024-10-10

申请号：US18743135

申请日：2024-06-14

Applicant: Lextar Electronics Corporation

Inventor： Yu-Jing FANG ,  Hsiang-Chun HSU ,  Cheng-Ping CHANG

IPC: H01L33/58 ,  H01L21/56 ,  H01L23/31 ,  H01L31/0203 ,  H01L31/0232 ,  H01L31/18 ,  H01L33/00 ,  H01L33/54

CPC classification number: H01L33/58 ,  H01L21/565 ,  H01L23/3135 ,  H01L31/0203 ,  H01L31/02327 ,  H01L31/18 ,  H01L33/005 ,  H01L33/54 ,  H01L2933/005 ,  H01L2933/0058

Abstract: A diode package structure includes a substrate, at least one diode chip and an opaque encapsulating layer. The substrate has an electrically conductive layer. At least one diode chip is mounted on the substrate and electrically connected to the electrically conductive layer. The opaque encapsulating layer has a cap portion and a sidewall portion, wherein the sidewall portion is connected to and surrounds the substrate to jointly form a concave structure, the cap portion is connected between a sidewall of the diode chip and the sidewall portion, wherein a first contact vertex of the cap portion and the sidewall of the diode chip is higher than a second contact vertex of the cap portion and the sidewall portion.

公开(公告)号：US20220190216A1

公开(公告)日：2022-06-16

申请号：US17447574

申请日：2021-09-13

Applicant: Lextar Electronics Corporation

Inventor： Yu-Jing FANG ,  Hsiang-Chun HSU ,  Cheng-Ping CHANG

IPC: H01L33/58 ,  H01L23/31 ,  H01L31/0203 ,  H01L31/0232 ,  H01L33/54 ,  H01L21/56 ,  H01L31/18 ,  H01L33/00

Abstract: A diode package structure includes a substrate, at least one diode chip and an opaque encapsulating layer. The substrate has an electrically conductive layer. At least one diode chip is mounted on the substrate and electrically connected to the electrically conductive layer. The opaque encapsulating layer has a cap portion and a sidewall portion, wherein the sidewall portion is connected to and surrounds the substrate to jointly form a concave structure, the cap portion is connected between a sidewall of the diode chip and the sidewall portion, wherein a first contact vertex of the cap portion and the sidewall of the diode chip is higher than a second contact vertex of the cap portion and the sidewall portion.