公开(公告)号：US20070093011A1

公开(公告)日：2007-04-26

申请号：US11163470

申请日：2005-10-20

申请人： Li-Shian Jeng ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng ,  Tzermin Shen ,  Da-Ching Cho

发明人： Li-Shian Jeng ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng ,  Tzermin Shen ,  Da-Ching Cho

IPC分类号： H01L21/8234

CPC分类号： H01L21/324 ,  H01L21/28167 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating a gate dielectric layer is described. First, a well is produced in a substrate. Later, the substrate is cleaned. Then the substrate is processed by a pre-annealed process. Afterwards, a gate dielectric layer is formed on the substrate. As a result, the on-current of the semiconductor device can be increased.

摘要翻译： 描述了制造栅介质层的方法。 首先，在底物中产生孔。 之后，清洗基板。 然后通过预退火工艺处理衬底。 之后，在基板上形成栅介质层。 结果，可以提高半导体器件的导通电流。

公开(公告)号：US07294541B2

公开(公告)日：2007-11-13

申请号：US11163470

申请日：2005-10-20

申请人： Li-Shian Jeng ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng ,  Tzermin Shen ,  Da-Ching Cho

发明人： Li-Shian Jeng ,  Tung-Hsing Lee ,  Tzyy-Ming Cheng ,  Tzermin Shen ,  Da-Ching Cho

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/324 ,  H01L21/28167 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of fabricating a gate dielectric layer is described. First, a well is produced in a substrate. Later, the substrate is cleaned. Then the substrate is processed by a pre-annealed process. Afterwards, a gate dielectric layer is formed on the substrate. As a result, the on-current of the semiconductor device can be increased.

摘要翻译： 描述了制造栅介质层的方法。 首先，在底物中产生孔。 之后，清洗基板。 然后通过预退火工艺处理衬底。 之后，在基板上形成栅介质层。 结果，可以提高半导体器件的导通电流。

公开(公告)号：US07288822B1

公开(公告)日：2007-10-30

申请号：US11399827

申请日：2006-04-07

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the lattice parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the lattice parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

摘要翻译： 公开了一种半导体结构，包括其中具有第一导电类型的第一阱和第二导电类型的第二阱的衬底，第一导电类型的第一MOS晶体管和第二导电类型的第二MOS晶体管。 第一MOS晶体管设置在第二阱上，包括在第二阱上的栅极结构和位于栅极结构旁边的第二阱中的开口中的第一导电类型的应变层。 开口底部附近的应变层的一部分的晶格参数与基板的晶格参数之间的差异小于开口底部以外的应变层的一部分的晶格参数之间的差异， 底物。 第二MOS晶体管设置在第一阱上。

公开(公告)号：US20070235770A1

公开(公告)日：2007-10-11

申请号：US11399827

申请日：2006-04-07

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

IPC分类号： H01L29/76

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

公开(公告)号：US07524716B2

公开(公告)日：2009-04-28

申请号：US11755669

申请日：2007-05-30

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

摘要翻译： 公开了一种半导体结构，包括其中具有第一导电类型的第一阱和第二导电类型的第二阱的衬底，第一导电类型的第一MOS晶体管和第二导电类型的第二MOS晶体管。 第一MOS晶体管设置在第二阱上，包括在第二阱上的栅极结构和位于栅极结构旁边的第二阱中的开口中的第一导电类型的应变层。 开口底部附近的应变层的一部分的单元参数与基板的单元参数之间的差值小于开口底部以外的应变层的一部分的单元参数之间的差， 底物。 第二MOS晶体管设置在第一阱上。

公开(公告)号：US20070275530A1

公开(公告)日：2007-11-29

申请号：US11308899

申请日：2006-05-24

申请人： Wen-Han Hung ,  Cheng-Tung Huang ,  Da-Ching Chiou ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzermin Shen ,  Tzyy-Ming Cheng

发明人： Wen-Han Hung ,  Cheng-Tung Huang ,  Da-Ching Chiou ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzermin Shen ,  Tzyy-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L29/665 ,  H01L29/6653

摘要： A semiconductor structure and a method of fabricating the same are provided. A substrate having a metal-oxide-semiconductor transistor is provided. The metal-oxide-semiconductor transistor includes a gate, a source/drain extended region, a first spacer, a liner, a source/drain and a metal silicide layer. A portion of the first spacer is removed to form a second spacer by performing an etching process. A contact etching stop layer is formed over the substrate.

摘要翻译： 提供半导体结构及其制造方法。 提供具有金属氧化物半导体晶体管的衬底。 金属氧化物半导体晶体管包括栅极，源极/漏极延伸区域，第一间隔物，衬垫，源极/漏极和金属硅化物层。 通过进行蚀刻处理，去除第一间隔物的一部分以形成第二间隔物。 接触蚀刻停止层形成在衬底上。

公开(公告)号：US20070238241A1

公开(公告)日：2007-10-11

申请号：US11755669

申请日：2007-05-30

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

摘要翻译： 公开了一种半导体结构，包括其中具有第一导电类型的第一阱和第二导电类型的第二阱的衬底，第一导电类型的第一MOS晶体管和第二导电类型的第二MOS晶体管。 第一MOS晶体管设置在第二阱上，包括在第二阱上的栅极结构和位于栅极结构旁边的第二阱中的开口中的第一导电类型的应变层。 开口底部附近的应变层的一部分的单元参数与基板的单元参数之间的差异小于与开口底部之间的应变层的一部分的单元参数之间的差， 底物。 第二MOS晶体管设置在第一阱上。

公开(公告)号：US07928512B2

公开(公告)日：2011-04-19

申请号：US11776562

申请日：2007-07-12

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

IPC分类号： H01L27/12

CPC分类号： H01L21/823412 ,  H01L21/823468 ,  H01L29/7842

摘要： A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.

摘要翻译： 本文提供了一种半导体器件，其包括具有第一型MOS晶体管，形成在其上的输入/输出（I / O）第二型MOS晶体管和核心第二型MOS晶体管的衬底。 半导体器件还包括第一应力层和第二应力层。 第一应力层设置在第一型MOS晶体管上或第一型MOS晶体管和I / O第二型MOS晶体管上。 第二应力层设置在芯型二次型MOS晶体管上。

公开(公告)号：US20080206942A1

公开(公告)日：2008-08-28

申请号：US11678627

申请日：2007-02-26

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Meng-Yi Wu ,  Tsai-Fu Hsiao ,  Shu-Yen Chan

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating strained-silicon transistors is disclosed. First, a semiconductor substrate is provided and a gate structure and a spacer surrounding the gate structure are disposed on the semiconductor substrate. A source/drain region is then formed in the semiconductor substrate around the spacer, and a first rapid thermal annealing process is performed to activate the dopants within the source/drain region. An etching process is performed to form a recess around the gate structure and a selective epitaxial growth process is performed to form an epitaxial layer in the recess. A second rapid thermal annealing process is performed to redefine the distribution of the dopants within the source/drain region and repair the damaged bonds of the dopants.

摘要翻译： 公开了制造应变硅晶体管的方法。 首先，提供半导体衬底，并且在半导体衬底上设置栅极结构和围绕栅极结构的间隔物。 然后在隔离物周围的半导体衬底中形成源极/漏极区域，并且执行第一快速热退火处理以激活源极/漏极区域内的掺杂剂。 执行蚀刻工艺以在栅极结构周围形成凹陷，并且执行选择性外延生长工艺以在凹部中形成外延层。 执行第二快速热退火处理以重新定义源/漏区域内的掺杂剂的分布并修复掺杂剂的损坏的键。

公开(公告)号：US20080020588A1

公开(公告)日：2008-01-24

申请号：US11459008

申请日：2006-07-20

申请人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Liang ,  Neng-Kuo Chen

发明人： Wen-Han Hung ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Liang ,  Neng-Kuo Chen

IPC分类号： H01L21/31

CPC分类号： H01L29/7833 ,  H01L21/823807 ,  H01L21/823835 ,  H01L27/092 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.

摘要翻译： 一种形成半导体器件的方法。 该方法包括以下步骤：提供具有形成在其上的第一晶体管，第二晶体管和非自对准硅化物器件的衬底，并且第一晶体管的导电类型与第二晶体管的导电类型不同。 在衬底上形成缓冲层，并在缓冲层上形成拉伸材料层。 第二晶体管上的拉伸材料层的一部分变薄，并且执行尖峰退火处理。 除去拉伸材料层以暴露衬底上的缓冲层，并且在非自对准硅化物器件上形成图案化的自对准硅化物阻挡层。 执行自对准处理以在第一晶体管和第二晶体管的一部分上形成自对准硅化物层。