Three-terminal cascade switch for controlling static power consumption in integrated circuits
    3.
    发明申请
    Three-terminal cascade switch for controlling static power consumption in integrated circuits 失效
    用于控制集成电路静态功耗的三端子级联开关

    公开(公告)号:US20070235784A1

    公开(公告)日:2007-10-11

    申请号:US11393259

    申请日:2006-03-30

    IPC分类号: H01L29/94

    摘要: A switching circuit configured for controlling static power consumption in integrated circuits includes a plurality of three-terminal, phase change material (PCM) switching devices connected between a voltage supply terminal and a corresponding sub-block of integrated circuit logic. Each of the PCM switching devices further includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

    摘要翻译: 配置成用于控制集成电路中的静态功耗的开关电路包括连接在电压源端子和集成电路逻辑的对应子块之间的多个三端子相变材料(PCM)开关器件。 每个PCM开关装置还包括设置在第一端子和第二端子之间接触的PCM,在第二端子和第三端子之间接触地设置的加热装置,加热装置位于PCM附近,并且被配置为将 PCM的可变形部分的电导率在较低电阻结晶状态和较高电阻无定形状态之间; 以及绝缘层,其被配置为将加热器与所述PCM材料电隔离,并且所述加热器与所述第一端子电隔离。 第一个PCM开关器件的第三个端子耦合到一个设置/复位开关,其余的PCM开关器件的第三个端子以级联配置耦合到相邻PCM开关器件的第二个端子。

    Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same
    6.
    发明申请
    Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same 失效
    包含两个或更多个直接选择性接触的耦合量子阱器件(CQWD)及其制造方法

    公开(公告)号:US20070145347A1

    公开(公告)日:2007-06-28

    申请号:US11315691

    申请日:2005-12-22

    IPC分类号: H01L29/06

    摘要: The present invention relates to a device structure that contains two or more conducting layers, two peripheral insulating layers, one or more intermediate insulating layers, and two or more conductive contacts. The two or more conducting layers are sandwiched between the two peripheral insulating layers, and they are spaced apart by the intermediate insulating layers to form two or more quantum wells. Each of the conductive contacts is directly and selectively connected with one of the conducting layers, so the individual quantum wells can be selectively accessed through the conductive contacts. Such a device structure preferably contains a coupled quantum well devices having two or more quantum wells that can be coupled together by inter-well tunneling effect at degenerate energy levels. More preferably, the device structure contains a memory cell having three quantum wells that can be arranged and constructed to define two different memory states.

    摘要翻译: 本发明涉及一种器件结构,其包含两个或多个导电层,两个外围绝缘层,一个或多个中间绝缘层以及两个或多个导电触点。 两个或更多个导电层夹在两个外围绝缘层之间,并且它们被中间绝缘层隔开以形成两个或更多个量子阱。 每个导电触点直接和选择性地连接到导电层中的一个,因此可以通过导电触点选择性地访问各个量子阱。 这样的器件结构优选地包含具有两个或更多个量子阱的耦合量子阱器件,所述量子阱可以在简并能级处通过阱间隧道效应耦合在一起。 更优选地,器件结构包含具有三个量子阱的存储单元,其可以被布置和构造以限定两个不同的存储器状态。