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公开(公告)号：US5313414A
公开(公告)日：1994-05-17
申请号：US976164
申请日：1992-11-12
Applicant: Lin Yang , Chun-Ling Liu
Inventor： Lin Yang , Chun-Ling Liu
CPC classification number: G06F17/5045 , G06F7/00
Abstract: A constant multiplier compiler model allows a modified canonical signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a modified canonical signed two's complement constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant is automatically generated by modifying a netlist of a precursor signed two's complement constant multiplier circuit for computing a product of the multi-bit multiplicand and a multi-bit constant that is all ones. The number of zeros in the multi-bit constant is first maximized by converting the constant to modified canonical form. Then, for each zero in the multi-bit constant, a corresponding logical column of full adders is deleted and each output signal of each adder so deleted is logically connected to a corresponding output signal in a preceding logical column of adders. Two exceptions to the foregoing rule occur. In the case of a first logical column of adders having no preceding logical column of adders, each output signal of each adder deleted is logically connected to a bit of the multi-bit multiplicand. In the case of a logical row of adders receiving a most significant bit of the multi-bit multiplicand, each output signal of each adder deleted is logically connected to one of the most significant bit of the multi-bit multiplicand and logic zero. The method produces a minimum layout, minimizing silicon cost, and produces a high performance design with critical paths optimized in terms of time delay.
Abstract translation: 常数乘法器编译器模型允许从用户规定的期望常数生成经修改的规范有符号二进制补码常数乘法器电路设计。 用于计算多位被乘数和多位常数的乘积的经修改的规范有符号二进制补码常数乘法器电路的网表通过修改前导符号二进制补码常数乘法器电路的网表来自动生成，用于计算 多位被乘数和多位常数，全为1。 通过将常数转换为修改的规范形式，多位常数中的零数首先最大化。 然后，对于多比特常数中的每个零，删除相应的完整加法器的逻辑列，并且如此删除的每个加法器的每个输出信号在逻辑上连接到前面的加法器逻辑列中的相应输出信号。 发生上述规则的两个例外。 在没有加法器的先前逻辑列的加法器的第一逻辑列的情况下，删除的每个加法器的每个输出信号逻辑上连接到多位被乘数的位。 在接收到多位被乘数的最高有效位的逻辑加法器行的情况下，删除的每个加法器的每个输出信号逻辑地连接到多位被乘数和逻辑零的最高有效位之一。 该方法产生最小布局，最大限度地降低硅成本，并产生具有在时间延迟方面优化的关键路径的高性能设计。
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公开(公告)号：US5424971A
公开(公告)日：1995-06-13
申请号：US983077
申请日：1992-11-12
Applicant: Lin Yang , Chun-Ling Liu
Inventor： Lin Yang , Chun-Ling Liu
CPC classification number: G06F17/5045 , G06F7/523
Abstract: A constant multiplier compiler model allows a constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant is automatically generated by modifying a netlist of a precursor constant multiplier circuit for computing a product of the multi-bit multiplicand and a multi-bit constant that is all ones. For each zero in the multi-bit constant, a corresponding logical column of full adders is deleted and each output signal of each adder so deleted is logically connected to a corresponding output signal in a preceding logical column of adders. Two exceptions to the foregoing rule occur. In the case of a first logical column of adders having no preceding logical column of adders, each output signal of each adder deleted is logically connected to a bit of the multi-bit multiplicand. In the case of a logical row of adders receiving a most significant bit of the multi-bit multiplicand, each output signal of each adder deleted is logically connected to one of the most significant bit of the multi-bit multiplicand and logic zero. The method produces a minimum layout, minimizing silicon cost, and produces a high performance design with critical paths optimized in terms of time delay.
Abstract translation: 恒定乘数编译器模型允许从用户指定所需常数生成恒定乘法器电路设计。 通过修改前兆常数乘法器电路的网表来自动产生用于计算多位被乘数和多比特常数的乘积的恒定乘法器电路的网表，用于计算多位被乘数和多位被乘数的乘积， 位常数是所有的。 对于多位常数中的每个零，删除相应的完整加法器的逻辑列，并将所删除的每个加法器的每个输出信号逻辑地连接到加法器的前一逻辑列中的相应输出信号。 发生上述规则的两个例外。 在没有加法器的先前逻辑列的加法器的第一逻辑列的情况下，删除的每个加法器的每个输出信号逻辑上连接到多位被乘数的位。 在接收到多位被乘数的最高有效位的逻辑加法器行的情况下，删除的每个加法器的每个输出信号逻辑地连接到多位被乘数和逻辑零的最高有效位之一。 该方法产生最小布局，最大限度地降低硅成本，并产生具有在时间延迟方面优化的关键路径的高性能设计。
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公开(公告)号：US5237597A
公开(公告)日：1993-08-17
申请号：US854525
申请日：1992-03-20
Applicant: Lin Yang , Chun-Ling Liu
Inventor： Lin Yang , Chun-Ling Liu
Abstract: An N-bit binary counter includes N 1-bit counters together producing an N-bit binary word, and a count enable signal generator for generating count enable signals for each of the N 1-bit counters. The count enable signal generator includes multiple logic group/carry ripple devices, different ones of which receive different numbers of bits of the binary word and generate count enable signals for the same number of bits. The logic group/carry ripple devices also receive a carry ripple output signal from an adjacent logic group/carry ripple device and generate a carry ripple output signal for another adjacent logic group/carry ripple device.
Abstract translation: N位二进制计数器包括N个1位计数器，一起产生一个N位二进制字，以及一个计数使能信号发生器，用于产生每个N 1比特计数器的计数使能信号。 计数使能信号发生器包括多个逻辑组/进位纹波器件，不同的逻辑组/进位纹波器件接收二进制字的不同位数并产生相同位数的计数使能信号。 逻辑组/进位纹波器件还接收来自相邻逻辑组/进位纹波器件的进位纹波输出信号，并为另一相邻逻辑组/进位纹波器件产生进位纹波输出信号。
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公开(公告)号：US5351206A
公开(公告)日：1994-09-27
申请号：US976233
申请日：1992-11-12
Applicant: Lin Yang , Chun-Ling Liu
Inventor： Lin Yang , Chun-Ling Liu
CPC classification number: G06F17/5045 , G06F7/523
Abstract: A constant multiplier compiler model allows a signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a signed two's complement constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant is automatically generated by modifying a netlist of a precursor signed two's complement constant multiplier circuit for computing a product of the multi-bit multiplicand and a multi-bit constant that is all ones. For each zero in the multi-bit constant, a corresponding logical column of full adders is deleted and each output signal of each adder so deleted is logically connected to a corresponding output signal in a preceding logical column of adders. Two exceptions to the foregoing rule occur. In the case of a first logical column of adders having no preceding logical column of adders, each output signal of each adder deleted is logically connected to a bit of the multi-bit multiplicand. In the case of a logical row of adders receiving a most significant bit of the multi-bit multiplicand, each output signal of each adder deleted is logically connected to one of the most significant bit of the multi-bit multiplicand and logic zero. The method produces a minimum layout, minimizing silicon cost, and produces a high performance design with critical paths optimized in terms of time delay.
Abstract translation: 恒定乘数编译器模型允许从用户指定所需常数生成带符号二进制补码常数乘法器电路设计。 用于计算多位被乘数和多比特常数乘积的有符号二进制补码常数乘法器电路的网表通过修改用于计算多比特乘法和多比特常数的乘积的前导符号二进制补码常数乘法器电路的网表自动生成， 位被乘数和多位常数，全部为1。 对于多位常数中的每个零，删除相应的完整加法器的逻辑列，并将所删除的每个加法器的每个输出信号逻辑地连接到加法器的前一逻辑列中的相应输出信号。 发生上述规则的两个例外。 在没有加法器的先前逻辑列的加法器的第一逻辑列的情况下，删除的每个加法器的每个输出信号逻辑上连接到多位被乘数的位。 在接收到多位被乘数的最高有效位的逻辑加法器行的情况下，删除的每个加法器的每个输出信号逻辑地连接到多位被乘数和逻辑零的最高有效位之一。 该方法产生最小布局，最大限度地降低硅成本，并产生具有在时间延迟方面优化的关键路径的高性能设计。
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公开(公告)号：US5258942A
公开(公告)日：1993-11-02
申请号：US854923
申请日：1992-03-20
Applicant: Chun-Ling Liu , Lin Yang
Inventor： Chun-Ling Liu , Lin Yang
CPC classification number: H03K19/21
Abstract: An apparatus for detecting a binary word each of the bits of which has the same binary value includes a plurality of logic groups, different ones of which receive different numbers of bits of the binary word. Each of the logic groups generates an output signal that is asserted if each of the number of bits received by the logic group has the same binary value. Carry ripple circuits series connected to form a carry ripple chain each receive an output signal from one of the logic groups. The carry ripple circuits also receive a carry ripple output signal from a previous carry ripple circuit and produce a carry ripple output signal for a succeeding carry ripple circuit. The carry ripple output signal is asserted when the output signal from the logic group is asserted and the carry ripple output signal from the previous carry ripple circuit is asserted.
Abstract translation: 用于检测其每个位具有相同二进制值的二进制字的装置包括多个逻辑组，其中不同的逻辑组接收二进制字的不同位数。 每个逻辑组产生一个输出信号，如果由逻辑组接收的每个比特数具有相同的二进制值，则该输出信号被断言。 携带波纹电路串联连接形成进位纹波链，每个接收来自逻辑组之一的输出信号。 进位纹波电路还接收来自先前进位纹波电路的进位纹波输出信号，并为后续的进位纹波电路产生进位纹波输出信号。 当来自逻辑组的输出信号被置位且来自前一个进位纹波电路的进位纹波输出信号被置位时，进位纹波输出信号被置位。
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Patent Agency Ranking
公开(公告)号：US5493525A
公开(公告)日：1996-02-20
申请号：US445505
申请日：1995-05-22
Applicant: Lin Yang , Chun-Ling Liu
Inventor： Lin Yang , Chun-Ling Liu
CPC classification number: G06F7/507
Abstract: Carry-chain structures useful in circuits such as adders, subtractors, counters and arithmetic logic units (i.e., ALU's). The carry-chain structures have regular architectures that can be conveniently generated in various bit widths by automated compiler systems. In a preferred embodiment, a method for automatically generating a carry-chain circuit using a compiler which includes a library of cells by selecting a first cell from the library of cells for use as a carry propagation cell, and using the first cell for multiplexing a carry signal produced by the carry propagation cell, such that the carry-chain includes a plurality of first cells. Further, a carry-chain architecture is produced using the aforementioned method.
Abstract translation: 在诸如加法器，减法器，计数器和算术逻辑单元（即ALU）的电路中有用的携带链结构。 携带链结构具有规则的架构，可以通过自动编译器系统方便地以各种位宽生成。 在优选实施例中，一种使用编译器自动生成携带链电路的方法，所述编译器包括通过从用于进位传播单元的单元库中选择第一单元的单元库，以及使用第一单元进行多路复用 携带信号由进位传播单元产生，使得携带链包括多个第一单元。 此外，使用上述方法制造携带链架构。
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公开(公告)号：US12155600B2
公开(公告)日：2024-11-26
申请号：US17235962
申请日：2021-04-21
Applicant: Zheng Liu , Xiaobo Zhang , Lin Yang
Inventor： Zheng Liu , Xiaobo Zhang , Lin Yang
IPC: H04L5/00 , H04W72/0453 , H04W72/23
Abstract: The present disclosure provides a method and a device for use in wireless communication node. The communication node transmits first information; herein, for a given SCS, the communication node assumes that X1 PRB(s) is (are) comprised in frequency-domain resources that can be occupied by the communication node for transmissions, X1 being a positive integer, and the X1 PRB(s) occupies (occupy) consecutive frequency-domain resources; a position of the X1 PRB(s) in frequency domain is related to at least one of whether the communication node is in coverage or a synchronization reference source selected by the communication node; the first information is used to indicate a position of the X1 PRB(s) in frequency domain, and the first information is transmitted via an air interface. The method in the present disclosure reduces interference and improves link and system performance.
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公开(公告)号：US12126438B2
公开(公告)日：2024-10-22
申请号：US17979776
申请日：2022-11-03
Applicant: Keying Wu , Xiaobo Zhang , Lin Yang
Inventor： Keying Wu , Xiaobo Zhang , Lin Yang
CPC classification number: H04L1/0038 , H04L5/0053 , H04L5/0094 , H04L27/2676 , H04W72/23
Abstract: The present disclosure provides a method and a device in a User Equipment (UE) and a base station for wireless communications. A UE receives first information, the first information being used for indicating M DCI blind decoding(s); monitors a first-type radio signal respectively on each of S sub-band(s) in a first time-domain resource; and performs at most M1 DCI blind decoding(s) of the M DCI blind decoding(s) on the S sub-band(s) in the first time-domain resource. Herein, the first-type radio signal detected on the S sub-band(s) is used for determining the M1 DCI blind decoding(s) out of the M DCI blind decoding(s). The above method allows the base station to make dynamic adjustments to the UE's blind decoding on PDCCH resources according to LBT results, ensuring that sufficient PDCCH resources are available and not too many PDSCH resources are preempted, and that excessive blind decodings can be avoided.
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9.发明授权公开(公告)号：US12052697B2
公开(公告)日：2024-07-30
申请号：US18195952
申请日：2023-05-11
Applicant: Zheng Liu , Xiaobo Zhang , Lin Yang
Inventor： Zheng Liu , Xiaobo Zhang , Lin Yang
IPC: H04W72/0446 , H04W48/12 , H04W72/232 , H04W72/50 , H04W74/00 , H04B17/382 , H04L47/70
CPC classification number: H04W72/0446 , H04W48/12 , H04W72/232 , H04W72/50 , H04W74/006 , H04B17/382 , H04L47/70 , H04L47/828
Abstract: A method and a device in a communication node for wireless communications are disclosed in the present disclosure. The communication node first receives a first signaling; and then receives a first radio signal in K1 slots and receives a second radio signal in K2 slots; the first signaling is used to determine the K1 and the K2; a first TB is used to generate the first radio signal, while a second TB is used to generate the second radio signal, the first TB comprising a positive integer number of bit(s), and the second TB comprising a positive integer number of bit(s); the K1 slots are divided into X1 slot groups, while the K2 slots are divided into X2 slot groups, and positions of the X1 slot groups and the X2 slot groups are interleaved in time domain. The present disclosure can reduce power consumption and improve coverage performance.
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10.发明授权公开(公告)号：US12052695B2
公开(公告)日：2024-07-30
申请号：US18122728
申请日：2023-03-17
Applicant: Zheng Liu , Xiaobo Zhang , Lin Yang
Inventor： Zheng Liu , Xiaobo Zhang , Lin Yang
IPC: H04W36/24 , H04L1/1607 , H04W72/0446 , H04W72/231 , H04W72/541 , H04L27/26 , H04N1/00
CPC classification number: H04W72/0446 , H04L1/1678 , H04W36/249 , H04W72/231 , H04W72/541 , H04L27/2666 , H04N1/00933
Abstract: The present disclosure provides a method and a device in a communication node for wireless communications. The communication node in the present disclosure first receives first information, and then transmits a first radio signal; a length of a time interval between a start time for transmitting the first radio signal and a first reference time is equal to a sum of a first timing adjustment and a second timing adjustment, the first timing adjustment being one of X candidate timing adjustments, the X being a positive integer greater than 1; the second timing adjustment is used for determining a transmission timing of a radio signal transmitted before the first radio signal in time domain; a transmitter of the first radio signal determines the first timing adjustment out of the X candidate timing adjustments by itself. The present disclosure can improve uplink synchronization performance.
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