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    INSPECTION STRUCTURE AND METHOD FOR IN-LINE MONITORING WAFER
    1.
    发明申请
    INSPECTION STRUCTURE AND METHOD FOR IN-LINE MONITORING WAFER 审中-公开
    用于在线监测波形的检查结构和方法

    公开(公告)号：US20100308220A1

    公开(公告)日：2010-12-09

    申请号：US12480117

    申请日：2009-06-08

    申请人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao ,  Hsi-Hua Liu ,  Shuen-Cheng Lei ,  Ming-Yi Lin

    发明人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao ,  Hsi-Hua Liu ,  Shuen-Cheng Lei ,  Ming-Yi Lin

    IPC分类号： G01N23/00

    CPC分类号： H01L22/12 ,  H01L22/34

    摘要： The method for in-line monitoring a wafer is described as follows. A wafer is provided, and at least one inspection structure is then formed on the wafer in the following steps. An N-well region and a P-well region are formed in the wafer, wherein the N-well region and the P-well region are separated from each other. A gate on each of the N-well region and the P-well region is formed. A P-type doped region is respectively formed in the N-well region and in the P-well region at both sides of the gates. A first contact plug is formed on each P-type doped region, and second contact plug is formed on each gate. Afterwards, a defect inspection is conducted utilizing an electron beam inspection (EBI) system, such that a short between each first contact plug and each gate is determined.

    摘要翻译： 在线监视晶片的方法如下所述。 提供晶片，然后在以下步骤中在晶片上形成至少一个检查结构。 在晶片中形成N阱区域和P阱区域，其中N阱区域和P阱区域彼此分离。 形成N阱区域和P阱区域中的每一个的栅极。 P型掺杂区域分别形成在栅极两侧的N阱区域和P阱区域中。 在每个P型掺杂区域上形成第一接触插塞，并且在每个栅极上形成第二接触插塞。 然后，利用电子束检查（EBI）系统进行缺陷检查，使得确定每个第一接触插塞和每个门之间的短路。

    METHOD OF FABRICATING TWO-STEP SELF-ALIGNED CONTACT
    5.
    发明申请
    METHOD OF FABRICATING TWO-STEP SELF-ALIGNED CONTACT 有权
    制造两步自对准接触的方法

    公开(公告)号：US20080230917A1

    公开(公告)日：2008-09-25

    申请号：US11686740

    申请日：2007-03-15

    申请人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao

    发明人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper hole self-aligned to and communicated with the lower hole is formed in the second dielectric layer, wherein the upper hole and the lower hole constitute a self-aligned contact hole. Afterwards, the self-aligned contact hole is filled with a conductive layer.

    摘要翻译： 提供一种制造自对准接触的方法。 在其中具有接触区域的基板上形成第一电介质层。 接下来，在第一电介质层中形成与接触区域对应的下孔。 此后，在第一电介质层上形成第二电介质层，然后在第二电介质层中形成自对准并与下孔连通的上孔，其中上孔和下孔构成自对准 接触孔。 然后，自对准接触孔填充有导电层。

    Method of fabricating two-step self-aligned contact
    7.
    发明授权
    Method of fabricating two-step self-aligned contact 有权
    制造两步自对准接触的方法

    公开(公告)号：US08129235B2

    公开(公告)日：2012-03-06

    申请号：US11686740

    申请日：2007-03-15

    申请人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao

    发明人： Ling-Chun Chou ,  Ming-Tsung Chen ,  Po-Chao Tsao

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/76831 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper hole self-aligned to and communicated with the lower hole is formed in the second dielectric layer, wherein the upper hole and the lower hole constitute a self-aligned contact hole. Afterwards, the self-aligned contact hole is filled with a conductive layer.

    摘要翻译： 提供一种制造自对准接触的方法。 在其中具有接触区域的基板上形成第一电介质层。 接下来，在第一电介质层中形成与接触区域对应的下孔。 此后，在第一电介质层上形成第二电介质层，然后在第二电介质层中形成自对准并与下孔连通的上孔，其中上孔和下孔构成自对准 接触孔。 然后，自对准接触孔填充有导电层。

    Fabricating method for a metal oxide semiconductor transistor
    9.
    发明授权
    Fabricating method for a metal oxide semiconductor transistor 有权
    金属氧化物半导体晶体管的制造方法

    公开(公告)号：US07595234B2

    公开(公告)日：2009-09-29

    申请号：US11532100

    申请日：2006-09-15

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： H01L21/336

    CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

    摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

    摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。

    FABRICATING METHOD FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR
    10.
    发明申请
    FABRICATING METHOD FOR A METAL OXIDE SEMICONDUCTOR TRANSISTOR 有权
    一种金属氧化物半导体晶体管的制造方法

    公开(公告)号：US20070066041A1

    公开(公告)日：2007-03-22

    申请号：US11532100

    申请日：2006-09-15

    申请人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    发明人： Po-Chao Tsao ,  Chang-Chi Huang ,  Ming-Tsung Chen ,  Yi-Yiing Chiang ,  Yu-Lan Chang ,  Chung-Ju Lee ,  Chih-Ning Wu ,  Kuan-Yang Liao

    IPC分类号： H01L21/4763

    CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/6659

    摘要： A method for forming a metal oxide semiconductor (MOS) transistor is provided. First, a gate structure is formed over a substrate. Then, offset spacers are formed on respective sidewalls of the gate structure. A first ion implantation process is performed to form a lightly doped drain (LDD) in the substrate beside the gate structure. Other spacers are formed on respective sidewalls of the offset spacers. Thereafter, a second ion implantation process is performed to form source/drain region in the substrate beside the spacers. Then, a metal silicide layer is formed on the surface of the source and the drain. An oxide layer is formed on the surface of the metal silicide layer. The spacers are removed and an etching stop layer is formed on the substrate. With the oxide layer over the metal silicide layer, the solvent for removing the spacers is prevented from damaging the metal silicide layer.

    摘要翻译： 提供一种用于形成金属氧化物半导体（MOS）晶体管的方法。 首先，在基板上形成栅极结构。 然后，在栅极结构的相应侧壁上形成偏移间隔物。 执行第一离子注入工艺以在栅极结构旁边的衬底中形成轻掺杂漏极（LDD）。 在偏置间隔物的相应侧壁上形成其它间隔物。 此后，进行第二离子注入工艺以在衬垫旁边的衬垫上形成源极/漏极区域。 然后，在源极和漏极的表面上形成金属硅化物层。 在金属硅化物层的表面上形成氧化物层。 去除间隔物，并在衬底上形成蚀刻停止层。 通过金属硅化物层上的氧化物层，可以防止用于除去间隔物的溶剂损坏金属硅化物层。