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公开(公告)号：US07394320B2
公开(公告)日：2008-07-01
申请号：US11584318
申请日：2006-10-20
IPC分类号： H03L7/00
摘要： A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a comparator, and a delay arrangement. The counter comprises a first input connected to the oscillator, a second input connected to a reference frequency terminal, and an output. An input of the comparator is connected to the output of the counter and an output of the comparator to the oscillator. The delay arrangement is connected between the oscillator and the first input of the counter or between the reference frequency terminal and the second input of the counter. The delay arrangement delays an input signal sent to an input of the delay arrangement, as a function of a sequence signal and makes a delayed signal available at an output of the delay arrangement.
摘要翻译： 公开了一种适用于移动无线电通信的锁相环路及其操作方法。 锁相环的一个实施例包括振荡器，计数器，比较器和延迟装置。 计数器包括连接到振荡器的第一输入端，连接到参考频率端子的第二输入端和输出端。 比较器的输入端连接到计数器的输出端和比较器的输出端连接到振荡器。 延迟装置连接在振荡器和计数器的第一输入端之间或连接在基准频率端子和计数器的第二输入端之间。 延迟装置将发送到延迟装置的输入的输入信号作为序列信号的函数进行延迟，并使延迟信号在延迟装置的输出处可用。
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公开(公告)号：US20070096833A1
公开(公告)日：2007-05-03
申请号：US11584318
申请日：2006-10-20
IPC分类号： H03L7/085
摘要： A phase-locked loop suitable for mobile radio communications and a method for operating the same is disclosed. One embodiment of the phase-locked loop comprises an oscillator, a counter, a comparator, and a delay arrangement. The counter comprises a first input connected to the oscillator, a second input connected to a reference frequency terminal, and an output. An input of the comparator is connected to the output of the counter and an output of the comparator to the oscillator. The delay arrangement is connected between the oscillator and the first input of the counter or between the reference frequency terminal and the second input of the counter. The delay arrangement delays an input signal sent to an input of the delay arrangement, as a function of a sequence signal and makes a delayed signal available at an output of the delay arrangement.
摘要翻译： 公开了一种适用于移动无线电通信的锁相环路及其操作方法。 锁相环的一个实施例包括振荡器，计数器，比较器和延迟装置。 计数器包括连接到振荡器的第一输入端，连接到参考频率端子的第二输入端和输出端。 比较器的输入端连接到计数器的输出端和比较器的输出端连接到振荡器。 延迟装置连接在振荡器和计数器的第一输入端之间或连接在基准频率端子和计数器的第二输入端之间。 延迟装置将发送到延迟装置的输入的输入信号作为序列信号的函数进行延迟，并使延迟信号在延迟装置的输出处可用。
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公开(公告)号：US08098104B2
公开(公告)日：2012-01-17
申请号：US12578105
申请日：2009-10-13
CPC分类号： H03L7/099 , H03B2200/0092 , H03L7/093 , H03L7/1976 , H03L2207/05
摘要： A device may include an oscillator circuit, a control circuit, a frequency detector circuit, and a processor circuit. The oscillator circuit may include a frequency control input to output an oscillator signal. The frequency of the oscillator signal depends on an input signal applied to the frequency control input. The control circuit is configured to apply a first input signal value, a second input signal value, and a third input signal value to the frequency control input. The frequency detector circuit is configured to detect the first frequency value of the oscillator signal when the first input signal value is applied to the frequency control input, a second frequency value of the oscillator signal when the second input signal value is applied to the frequency control input, and a third frequency value of the oscillator signal when the third input signal value is applied to the frequency control input.
摘要翻译： 设备可以包括振荡器电路，控制电路，频率检测器电路和处理器电路。 振荡器电路可以包括用于输出振荡器信号的频率控制输入。 振荡器信号的频率取决于施加到频率控制输入的输入信号。 控制电路被配置为向频率控制输入施加第一输入信号值，第二输入信号值和第三输入信号值。 频率检测器电路被配置为当第一输入信号值被施加到频率控制输入时检测振荡器信号的第一频率值，当第二输入信号值被施加到频率控制时，振荡器信号的第二频率值 输入和第三频率值，当第三输入信号值被施加到频率控制输入时。
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4.发明授权Phase/frequency detector, phase locked loop, method for phase/frequency detection and method for generating an oscillator signal 有权相位/频率检测器，锁相环，相位/频率检测方法以及产生振荡器信号的方法公开(公告)号：US07592874B2
公开(公告)日：2009-09-22
申请号：US11925539
申请日：2007-10-26
CPC分类号： H03L7/085 , H03D13/001 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.
摘要翻译： 相位/频率检测器具有模计数器，用于根据振荡器信号输出具有预定字长的计数器字。 另外，提供了用于输出具有作为通道字的积分的函数的预定字长的积分器字的模积分器。 相位/频率检测器还具有差分元件，用于输出具有预定字长的相位误差字作为计数器字和积分器字之差的函数。
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5.发明申请Phase Locked Loop, Transceiver Device and Method for Generating an Oscillator Signal 有权锁相环，收发器装置和产生振荡器信号的方法公开(公告)号：US20080106341A1
公开(公告)日：2008-05-08
申请号：US11925379
申请日：2007-10-26
摘要： A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
摘要翻译： 锁相环具有受控振荡器，用于根据控制信号输出振荡器信号。 比较器从参考频率信号和从振荡器信号导出的反馈信号之间的比较产生比较结果。 锁相环还具有用于对比较结果进行滤波和从比较结果导出控制信号的滤波器块，其中滤波器块具有环路滤波器和用于至少一个第一干扰频率的频率选择衰减的抑制滤波器 在比较结果中。
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6.发明申请PHASE/FREQUENCY DETECTOR, PHASE LOCKED LOOP, METHOD FOR PHASE/FREQUENCY DETECTION AND METHOD FOR GENERATING AN OSCILLATOR SIGNAL 有权相位/频率检测器，相位锁定环路，相位/频率检测方法及产生振荡器信号的方法公开(公告)号：US20080100386A1
公开(公告)日：2008-05-01
申请号：US11925539
申请日：2007-10-26
CPC分类号： H03L7/085 , H03D13/001 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A phase/frequency detector has a modulo counter for outputting a counter word with a predetermined word length depending on an oscillator signal. In addition, a modulo integrator for outputting an integrator word with the predetermined word length as a function of integration of a channel word is provided. The phase/frequency detector also has a difference element for outputting a phase error word with the predetermined word length as a function of a difference between the counter word and the integrator word.
摘要翻译： 相位/频率检测器具有模计数器，用于根据振荡器信号输出具有预定字长的计数器字。 另外，提供了用于输出具有作为通道字的积分的函数的预定字长的积分器字的模积分器。 相位/频率检测器还具有差分元件，用于输出具有预定字长的相位误差字作为计数器字和积分器字之差的函数。
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7.再颁专利Phase locked loop, transceiver device and method for generating an oscillator signal 有权锁相环，收发器装置和用于产生振荡器信号的方法公开(公告)号：USRE44879E1
公开(公告)日：2014-05-06
申请号：US13440521
申请日：2012-04-05
IPC分类号： H03L7/00
摘要： A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
摘要翻译： 锁相环具有受控振荡器，用于根据控制信号输出振荡器信号。 比较器从参考频率信号和从振荡器信号导出的反馈信号之间的比较产生比较结果。 锁相环还具有用于对比较结果进行滤波和从比较结果导出控制信号的滤波器块，其中滤波器块具有环路滤波器和用于至少一个第一干扰频率的频率选择衰减的抑制滤波器 在比较结果中。
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8.发明授权Phase locked loop, transceiver device and method for generating an oscillator signal 有权锁相环，收发器装置和用于产生振荡器信号的方法公开(公告)号：US07692498B2
公开(公告)日：2010-04-06
申请号：US11925379
申请日：2007-10-26
IPC分类号： H03L7/00
摘要： A phase locked loop has a controlled oscillator for outputting an oscillator signal depending on a control signal. A comparator generates a comparison result from a comparison between a reference frequency signal and a feedback signal derived from the oscillator signal. The phase locked loop also has a filter block for filtering the comparison result and for deriving the control signal from the comparison result, where the filter block has a loop filter and a rejection filter for the frequency-selective attenuation of at least one first interference frequency in the comparison result.
摘要翻译： 锁相环具有受控振荡器，用于根据控制信号输出振荡器信号。 比较器从参考频率信号和从振荡器信号导出的反馈信号之间的比较产生比较结果。 锁相环还具有用于对比较结果进行滤波和从比较结果导出控制信号的滤波器块，其中滤波器块具有环路滤波器和用于至少一个第一干扰频率的频率选择衰减的抑制滤波器 在比较结果中。
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9.发明申请Digital phase locked loop, method for controlling a digital phase locked loop and method for generating an oscillator signal 审中-公开数字锁相环，用于控制数字锁相环的方法和产生振荡信号的方法公开(公告)号：US20070008040A1
公开(公告)日：2007-01-11
申请号：US11477262
申请日：2006-06-29
IPC分类号： H03L7/085
CPC分类号： H03L7/1976 , H03K23/667 , H03L7/091 , H03L7/093 , H03L7/099 , H03L2207/50
摘要： A digital phase locked loop includes a digital phase detector, a downstream digital filter and an oscillator. In addition, a frequency divider resides in a feedback path and has an actuating input for setting a divider ratio, the input of which is connected to the oscillator and the phase detector. The phase locked loop comprises a sigma-delta modulator having a data input for supplying a data word and having an actuating output for supplying a frequency setting word to the actuating input of the frequency divider. The data word is configured such that the sigma-delta modulator generates jitter in the frequency setting word, with the result that the signal which is applied to the feedback input of the phase detector is not constant over a relatively long period of time.
摘要翻译： 数字锁相环包括数字相位检测器，下游数字滤波器和振荡器。 此外，分频器驻留在反馈路径中，并且具有用于设置分频比的致动输入，其输入连接到振荡器和相位检测器。 锁相环包括具有用于提供数据字的数据输入并具有用于向频率分配器的致动输入提供频率设定字的致动输出的Σ-Δ调制器。 数据字被配置为使得Σ-Δ调制器在频率设置字中产生抖动，结果是施加到相位检测器的反馈输入的信号在相对长的时间段内不是恒定的。
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公开(公告)号：US08598929B1
公开(公告)日：2013-12-03
申请号：US13664536
申请日：2012-10-31
申请人： Christian Wicpalek , Thomas Mayer
发明人： Christian Wicpalek , Thomas Mayer
IPC分类号： H03L7/06
CPC分类号： H03L7/1075 , H03L7/093 , H03L7/095 , H03L7/101 , H03L7/104
摘要： The disclosed invention relates to a digital phase locked loop having a switchable digital loop filter configured to selectively operate at different levels of resolution. The digital phase locked loop has a phase frequency detector that determines a phase difference between a reference signal and a feedback signal and to convert the phase difference to a digital word. A digital loop filter filters the digital word to generate a control word. A bit shift network modifies the digital word in a manner that switches the resolution of the digital loop filter between two or more distinct resolution states that comprise a bit sequence located at different positions in the digital word. The two or more distinct resolution states allow the digital loop filter to provide a low resolution (high amplitude) for a settling state of operation and a high resolution (low amplitude) for a locked state of operation.
摘要翻译： 所公开的本发明涉及一种具有可切换数字环路滤波器的数字锁相环，其被配置为选择性地以不同的分辨率水平进行操作。 数字锁相环具有相位频率检测器，其确定参考信号和反馈信号之间的相位差，并将相位差转换为数字字。 数字环路滤波器对数字字进行滤波以产生控制字。 位移网络以使数字环路滤波器的分辨率在两个或多个不同分辨率状态之间切换的方式修改数字字，该状态包括位于数字字中的不同位置的位序列。 两个或更多个不同的分辨率状态允许数字环路滤波器为操作的建立状态提供低分辨率（高幅度），并且对于锁定操作状态提供高分辨率（低幅度）。
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