公开(公告)号：US12067262B2

公开(公告)日：2024-08-20

申请号：US17895737

申请日：2022-08-25

Applicant: Lodestar Licensing Group, LLC

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/00 ,  G06F21/60 ,  G06F21/79

CPC classification number: G06F3/0622 ,  G06F3/0659 ,  G06F3/0679 ,  G06F21/602 ,  G06F21/79

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

公开(公告)号：US20240361924A1

公开(公告)日：2024-10-31

申请号：US18769926

申请日：2024-07-11

Applicant: Lodestar Licensing Group, LLC

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F3/06 ,  G06F21/60 ,  G06F21/79

CPC classification number: G06F3/0622 ,  G06F3/0659 ,  G06F3/0679 ,  G06F21/602 ,  G06F21/79

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

公开(公告)号：US12118248B2

公开(公告)日：2024-10-15

申请号：US18206934

申请日：2023-06-07

Applicant: Lodestar Licensing Group, LLC

Inventor： Sebastien Andre Jean

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0649 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/068 ,  G11C16/0483 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

公开(公告)号：US20240118831A1

公开(公告)日：2024-04-11

申请号：US18206934

申请日：2023-06-07

Applicant: Lodestar Licensing Group, LLC

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0649 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/068 ,  G11C16/0483 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

公开(公告)号：US11983106B2

公开(公告)日：2024-05-14

申请号：US17869313

申请日：2022-07-20

Applicant: Lodestar Licensing Group, LLC

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/14

CPC classification number: G06F12/0246 ,  G06F3/0623 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0292 ,  G06F12/1408 ,  G06F2212/7201

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

公开(公告)号：US20250036318A1

公开(公告)日：2025-01-30

申请号：US18914857

申请日：2024-10-14

Applicant: Lodestar Licensing Group, LLC

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.