利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

45 条记录 (耗时 0.031 秒)

    Power-aware line intervention for a multiprocessor directory-based coherency protocol
    4.
    发明申请
    Power-aware line intervention for a multiprocessor directory-based coherency protocol 审中-公开
    基于多处理器目录的一致性协议的功率感知线路干预

    公开(公告)号：US20090138220A1

    公开(公告)日：2009-05-28

    申请号：US11946551

    申请日：2007-11-28

    申请人： Robert H. Bell, JR. ,  Louis B. Capps, JR. ,  Thomas E. Cook ,  Michael J. Shapiro ,  Naresh Nayar

    发明人： Robert H. Bell, JR. ,  Louis B. Capps, JR. ,  Thomas E. Cook ,  Michael J. Shapiro ,  Naresh Nayar

    IPC分类号： G01R21/02 ,  G06F12/08

    CPC分类号： G06F12/0817 ,  Y02D10/13

    摘要： A directory-based coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.

    摘要翻译： 基于目录的一致性方法，系统和程序被提供用于基于每个存储器源处的感测温度或功率耗散值来在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。 通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存 通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

    Power-aware line intervention for a multiprocessor snoop coherency protocol
    5.
    发明授权
    Power-aware line intervention for a multiprocessor snoop coherency protocol 有权
    多处理器侦听一致性协议的功率感知线路干预

    公开(公告)号：US07870337B2

    公开(公告)日：2011-01-11

    申请号：US11946249

    申请日：2007-11-28

    申请人： Robert H. Bell, Jr. ,  Louis B. Capps, Jr. ,  Thomas E. Cook ,  Michael J. Shapiro ,  Naresh Nayar

    发明人： Robert H. Bell, Jr. ,  Louis B. Capps, Jr. ,  Thomas E. Cook ,  Michael J. Shapiro ,  Naresh Nayar

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G01R21/00 ,  G01R21/06 ,  G01R19/00

    CPC分类号： G06F12/0831 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.

    摘要翻译： 提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。 通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存 通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

    Power-aware line intervention for a multiprocessor snoop coherency protocol
    6.
    发明申请
    Power-aware line intervention for a multiprocessor snoop coherency protocol 有权
    多处理器侦听一致性协议的功率感知线路干预

    公开(公告)号：US20090138660A1

    公开(公告)日：2009-05-28

    申请号：US11946249

    申请日：2007-11-28

    申请人： Robert H. Bell, JR. ,  Louis B. Capps, JR. ,  Thomas E. Cook ,  Michael J. Shapiro ,  Naresh Nayar

    发明人： Robert H. Bell, JR. ,  Louis B. Capps, JR. ,  Thomas E. Cook ,  Michael J. Shapiro ,  Naresh Nayar

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831 ,  G06F2212/1028 ,  Y02D10/13

    摘要： A snoop coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.

    摘要翻译： 提供窥探一致性方法，系统和程序，用于基于每个存储器源处的感测温度或功率耗散值，在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。 通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存 通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

    Power grid structure to optimize performance of a multiple core processor
    8.
    发明授权
    Power grid structure to optimize performance of a multiple core processor 失效
    电网结构优化多核处理器的性能

    公开(公告)号：US07667470B2

    公开(公告)日：2010-02-23

    申请号：US12143911

    申请日：2008-06-23

    申请人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

    发明人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

    IPC分类号： G01R31/08 ,  G06F19/00

    CPC分类号： G06F1/3203 ,  G06F1/26 ,  G06F1/3296 ,  H01L23/50 ,  H01L2924/0002 ,  Y02D10/172 ,  H01L2924/00

    摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.

    摘要翻译： 减少数量的电压调节器模块为封装提供了减少的电源电压数量。 该封装包括用于每个电压调节器模块的电压平面。 管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。 晶圆级测试确定优化每个核心或其他组件的性能的电压。 给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。 数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。 工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。

    Power grid structure to optimize performance of a multiple core processor
    9.
    发明授权
    Power grid structure to optimize performance of a multiple core processor 失效
    电网结构优化多核处理器的性能

    公开(公告)号：US07420378B2

    公开(公告)日：2008-09-02

    申请号：US11456658

    申请日：2006-07-11

    申请人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

    发明人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

    IPC分类号： G01R31/08 ,  G06F19/00

    CPC分类号： G06F1/3203 ,  G06F1/26 ,  G06F1/3296 ,  H01L23/50 ,  H01L2924/0002 ,  Y02D10/172 ,  H01L2924/00

    摘要： A reduced number of voltage regulator modules provides a reduced number of supply voltages to the package. The package includes a voltage plane for each of the voltage regulator modules. Each core or other component on the die is tied to a switch on the package, and each switch is electrically connected to all of the voltage planes. A wafer-level test determines a voltage that optimizes performance of each core or other component. Given these voltage values, an engineer may determine voltage settings for the voltage regulator modules and which cores are to be connected to which voltage regulator modules. A database stores voltage setting data, such as the optimal voltage for each component, switch values, or voltage settings for each voltage regulator module. An engineering wire may permanently set each switch to customize the voltage supply to each core or other component.

    摘要翻译： 减少数量的电压调节器模块为封装提供了减少的电源电压数量。 该封装包括用于每个电压调节器模块的电压平面。 管芯上的每个核心或其他部件连接到封装上的开关，并且每个开关电连接到所有电压平面。 晶圆级测试确定优化每个核心或其他组件的性能的电压。 给定这些电压值，工程师可以确定电压调节器模块的电压设置以及要连接到哪些电压调节器模块的哪些核心。 数据库存储电压设置数据，例如每个组件的最佳电压，开关值或每个电压调节器模块的电压设置。 工程线可以永久地设置每个开关以定制每个芯或其他部件的电压供应。

    Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip
    10.
    发明授权
    Apparatus and method for customized burn-in of cores on a multicore microprocessor integrated circuit chip 失效
    在多核微处理器集成电路芯片上定制化核心的装置和方法

    公开(公告)号：US07268570B1

    公开(公告)日：2007-09-11

    申请号：US11426646

    申请日：2006-06-27

    申请人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Joanne Ferris ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

    发明人： Jean Audet ,  Louis B. Capps, Jr. ,  Glenn G. Daves ,  Joanne Ferris ,  Anand Haridass ,  Ronald E. Newhart ,  Michael J. Shapiro

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2855

    摘要： An apparatus and method for providing a multi-core integrated circuit chip that reduces the cost of the package and board while optimizing performance of the cores for use with a single voltage plane. The apparatus and method of the illustrative embodiments make use of a dynamic burn-in technique that optimizes all of the cores on the chip to run at peak performance at a single voltage. Each core is burned-in with a customized burn-in voltage that provides uniform power and performance across the whole chip. This results in a higher burn-in yield and lower overall power in the integrated circuit chip. The optimization of the cores to run at peak performance at a single voltage is achieved through use of the negative bias temperature instability affects on the cores imparted by the burn-in voltages applied.

    摘要翻译： 一种用于提供多核集成电路芯片的装置和方法，其降低了封装和板的成本，同时优化用于单个电压平面的芯的性能。 说明性实施例的装置和方法使用动态老化技术，其优化芯片上的所有核心以在单个电压下以峰值性能运行。 每个核心都具有定制的老化电压，可在整个芯片上提供均匀的功率和性能。 这导致集成电路芯片中更高的老化成本和更低的总功率。 通过使用负偏置温度不稳定性影响由所施加的老化电压施加的磁芯，可以实现在单电压下以峰值性能运行的磁芯的优化。