公开(公告)号：US07318182B2

公开(公告)日：2008-01-08

申请号：US11002692

申请日：2004-12-02

申请人： Louis Bernard Bushard ,  Sang Hoo Dhong ,  Brian King Flachs ,  Osamu Takahashi ,  Michael Brian White

发明人： Louis Bernard Bushard ,  Sang Hoo Dhong ,  Brian King Flachs ,  Osamu Takahashi ,  Michael Brian White

IPC分类号： G01R31/28

CPC分类号： G11C29/08 ,  G11C7/20 ,  G11C2029/0407

摘要： The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.

摘要翻译： 本发明提供了一种用于存储器阵列校验的方法。 接收初始化命令，并根据接收到的初始化命令生成内存阵列初始化设置。 存储器阵列初始化设置存储在存储器阵列中。 识别存储器阵列的确定性读输出功能，并且基于所识别的确定性读输出功能来执行存储器阵列上的逻辑内置自检扫描。

公开(公告)号：US08117579B2

公开(公告)日：2012-02-14

申请号：US12023337

申请日：2008-01-31

申请人： James Douglas Warnock ,  Wendel Dieter ,  David E. Lackey ,  William Vincent Huott ,  Leon Jacob Sigal ,  Louis Bernard Bushard ,  Sang Hoo Dhong

发明人： James Douglas Warnock ,  Wendel Dieter ,  David E. Lackey ,  William Vincent Huott ,  Leon Jacob Sigal ,  Louis Bernard Bushard ,  Sang Hoo Dhong

IPC分类号： G06F17/50

CPC分类号： G01R31/318594 ,  G01R31/318552

摘要： A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

摘要翻译： 提供了一种方法，系统和程序，用于使用中间时钟信号和一个或多个第一模式控制信号从一般扫描设计（GSD）时钟缓冲器产生电平敏感扫描设计（LSSD）时钟信号，以产生多个LSSD时钟信号 从GSD时钟缓冲器的输出部分接收中间时钟信号和第一模式控制信号，其中GSD时钟缓冲器还被配置为响应于接收到GSD模式产生多个GSD时钟信号，产生 来自GSD时钟缓冲器的输入部分的中间时钟信号响应于接收GSD模式信号。

公开(公告)号：US20090199036A1

公开(公告)日：2009-08-06

申请号：US12023337

申请日：2008-01-31

申请人： James D. Warnock ,  Wendel Dieter ,  David E. Lackey ,  William Vincent Huott ,  Leon Jacob Sigal ,  Louis Bernard Bushard ,  Sang Hoo Dhong

发明人： James D. Warnock ,  Wendel Dieter ,  David E. Lackey ,  William Vincent Huott ,  Leon Jacob Sigal ,  Louis Bernard Bushard ,  Sang Hoo Dhong

IPC分类号： G06F1/00

CPC分类号： G01R31/318594 ,  G01R31/318552

摘要： A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.

摘要翻译： 提供了一种方法，系统和程序，用于使用中间时钟信号和一个或多个第一模式控制信号从一般扫描设计（GSD）时钟缓冲器产生电平敏感扫描设计（LSSD）时钟信号，以产生多个LSSD时钟信号 从GSD时钟缓冲器的输出部分接收中间时钟信号和第一模式控制信号，其中GSD时钟缓冲器还被配置为响应于接收GSD模式产生多个GSD时钟信号，产生 来自GSD时钟缓冲器的输入部分的中间时钟信号响应于接收GSD模式信号。

公开(公告)号：US07844869B2

公开(公告)日：2010-11-30

申请号：US12015254

申请日：2008-01-16

申请人： Louis Bernard Bushard ,  Todd Alan Christensen ,  Jesse Daniel Smith

发明人： Louis Bernard Bushard ,  Todd Alan Christensen ,  Jesse Daniel Smith

IPC分类号： G01R31/28

CPC分类号： G01R31/3187

摘要： A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.

摘要翻译： 一种包括存储器阵列和逻辑的电路路径的方法和电路实现测试，包括逻辑内置自测（LBIST）诊断，以及提供了主题电路所在的设计结构。 电路路径的测试包括用初始化模式初始化电路路径中的存储器阵列，切换到逻辑内置自测（LBIST）模式，并为存储器阵列提供只读模式，并运行逻辑内置自检（LBIST） ）测试电路路径。

公开(公告)号：US07733722B2

公开(公告)日：2010-06-08

申请号：US12351908

申请日：2009-01-12

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

IPC分类号： G11C7/00

CPC分类号： G11C29/12 ,  G11C17/165 ,  G11C17/18 ,  G11C29/026 ,  G11C29/027

摘要： Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

摘要翻译： 设备可实现对eFuse的读出放大器的有效测试，而无需对eFuse进行编程或打击。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

公开(公告)号：US20080250290A1

公开(公告)日：2008-10-09

申请号：US12139114

申请日：2008-06-13

申请人： Louis Bernard Bushard ,  Nathan Paul Chelstrom ,  Naoki Kiryu ,  David John Krolak

发明人： Louis Bernard Bushard ,  Nathan Paul Chelstrom ,  Naoki Kiryu ,  David John Krolak

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318525 ,  G01R31/3187

摘要： A method and apparatus for loading a ring of non-scan latches for a logic built-in self-test. A logic built-in self-test value is loaded into a scannable latch from the logic built-in self-test. An override control signal is asserted in response to loading the logic built-in self-test value into the scannable latch. A non-scan latch is forced to load the logic built-in self-test value from the scannable latch in response to asserting the override control signal. Logic paths in the ring of non-scan latches are exercised. The non-scan latch is part of the logical paths. The test results are captured from the logic paths and the test results are compared against expected test results to determine if the logic paths within the ring of non-scan latches are functioning properly.

摘要翻译： 一种用于加载用于逻辑内置自检的非扫描锁存器环的方法和装置。 逻辑内置自检值从逻辑内置自检中加载到可扫描锁存器中。 响应于将逻辑内置自检值加载到可扫描锁存器中，覆盖控制信号被断言。 响应于断言覆盖控制信号，非扫描锁存器被强制从可扫描锁存器加载逻辑内置自检值。 执行非扫描锁存器环中的逻辑路径。 非扫描锁存器是逻辑路径的一部分。 从逻辑路径捕获测试结果，并将测试结果与预期测试结果进行比较，以确定非扫描锁存器环内的逻辑路径是否正常工作。

公开(公告)号：US20080169843A1

公开(公告)日：2008-07-17

申请号：US11872763

申请日：2007-10-16

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

IPC分类号： G01R19/00

CPC分类号： G11C17/18 ,  G01R31/07 ,  G11C17/165 ,  G11C29/02 ,  G11C29/026 ,  G11C29/027

摘要： A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

摘要翻译： 一种用于eFuse的读出放大器的有效测试的方法和装置，而不必对eFuse进行编程或打击，并且提供了一个设在该电路中的设计结构。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

公开(公告)号：US20090063921A1

公开(公告)日：2009-03-05

申请号：US11845829

申请日：2007-08-28

申请人： Anthony Gus Aipperspach ,  Louis Bernard Bushard ,  Dennis Thomas Cox

发明人： Anthony Gus Aipperspach ,  Louis Bernard Bushard ,  Dennis Thomas Cox

IPC分类号： G06F11/27 ,  G01R31/3187

CPC分类号： G06F11/27 ,  G01R31/31721 ,  G01R31/318575 ,  G01R31/3187

摘要： A method, device and system for performing on-chip testing are presented. In particular, the present invention provides a method, device and system for reducing noise due to large changes in current that occur during logical built-in self testing (LBIST) operations in integrated circuits. The method includes executing a first logical built-in self test sequence for a first logic region within an integrated circuit, subsequently executing a second logical built-in self test sequence for a second logic region within the integrated circuit, wherein the second test sequence is offset from the first test sequence by one or more clock cycles.

摘要翻译： 提出了一种用于执行片上测试的方法，设备和系统。 特别地，本发明提供了一种用于在集成电路中的逻辑内置自检（LBIST）操作期间发生的大电流变化来降低噪声的方法，装置和系统。 该方法包括为集成电路内的第一逻辑区域执行第一逻辑内置自检序列，随后对集成电路内的第二逻辑区域执行第二逻辑内置自测序列，其中第二测试序列为 从第一个测试序列偏移一个或多个时钟周期。

公开(公告)号：US07489572B2

公开(公告)日：2009-02-10

申请号：US11622519

申请日：2007-01-12

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

IPC分类号： G11C7/00

CPC分类号： G11C29/12 ,  G11C17/165 ,  G11C17/18 ,  G11C29/026 ,  G11C29/027

摘要： A method implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

摘要翻译： 一种方法实现对eFuse的读出放大器的有效测试，而不必对eFuse进行编程或打击。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。

公开(公告)号：US20080170449A1

公开(公告)日：2008-07-17

申请号：US11622519

申请日：2007-01-12

申请人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

发明人： Anthony Gus Aipperspach ,  David Howard Allen ,  Louis Bernard Bushard ,  Phil Christopher Felice Paone ,  Gregory John Uhlmann

IPC分类号： G11C29/00

CPC分类号： G11C29/12 ,  G11C17/165 ,  G11C17/18 ,  G11C29/026 ,  G11C29/027

摘要： A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

摘要翻译： 一种用于eFuse的读出放大器的有效测试的方法和装置，而不必对eFuse进行编程或打击。 在读出放大器的初始处理之后，测试在编程eFuse之前确定读出放大器是否能够产生有效的“0”和“1”。 分别驱动通常分别将真实感测节点和补偿感测节点预充电到高电压的第一预充电装置和第二预充电装置。 为了测试，预充电器件中的一个有条件地被保持以保证读出放大器的结果为“0”和“1”。 这允许检测放大器设备以及下行流连接设备的测试。 一旦测试完成，两个预充电装置就一起进行控制。