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公开(公告)号:US20100194462A1
公开(公告)日:2010-08-05
申请号:US12364304
申请日:2009-02-02
申请人: Luca Petruzzi , Paolo Del Croce , Markus Ladurner , Bernhard Meldt , Adrian Apostol , Vasile Matei
发明人: Luca Petruzzi , Paolo Del Croce , Markus Ladurner , Bernhard Meldt , Adrian Apostol , Vasile Matei
IPC分类号: H03K17/687
CPC分类号: H03K17/0822
摘要: Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.
摘要翻译: 公开了电流控制电路的电路,系统和方法。 在一个实施例中,控制电路包括第一MOS晶体管和第二MOS晶体管。 第一和第二MOS晶体管的第一源极/漏极耦合到电源的输出端。 第一MOS晶体管的第二源/漏耦合到电流控制电路的第一输出节点。 第二MOS晶体管的第二源/漏耦合到电流控制电路的第二输出节点。 控制电路还包括阻止电流从电流控制电路的第一输出节点流到电流控制电路的第二输出节点的装置。
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公开(公告)号:US07911260B2
公开(公告)日:2011-03-22
申请号:US12364304
申请日:2009-02-02
申请人: Luca Petruzzi , Paolo Del Croce , Markus Ladurner , Bernhard Meldt , Adrian Apostol , Vasile Matei
发明人: Luca Petruzzi , Paolo Del Croce , Markus Ladurner , Bernhard Meldt , Adrian Apostol , Vasile Matei
IPC分类号: G05F1/10
CPC分类号: H03K17/0822
摘要: Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.
摘要翻译: 公开了电流控制电路的电路,系统和方法。 在一个实施例中,控制电路包括第一MOS晶体管和第二MOS晶体管。 第一和第二MOS晶体管的第一源极/漏极耦合到电源的输出端。 第一MOS晶体管的第二源/漏耦合到电流控制电路的第一输出节点。 第二MOS晶体管的第二源/漏耦合到电流控制电路的第二输出节点。 控制电路还包括阻止电流从电流控制电路的第一输出节点流到电流控制电路的第二输出节点的装置。
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公开(公告)号:US07098691B2
公开(公告)日:2006-08-29
申请号:US10899020
申请日:2004-07-27
申请人: Zvi Or-Bach , Petrica Avram , Romeo Iacobut , Adrian Apostol , Ze'ev Wurman , Adam Leventhal , Richard Zeman
发明人: Zvi Or-Bach , Petrica Avram , Romeo Iacobut , Adrian Apostol , Ze'ev Wurman , Adam Leventhal , Richard Zeman
IPC分类号: H03K19/173
CPC分类号: H03K19/1776 , G01R31/3172 , G01R31/318516 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17796 , H01L2924/00
摘要: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
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公开(公告)号:US20070080709A1
公开(公告)日:2007-04-12
申请号:US11246294
申请日:2005-10-11
申请人: Zvi Or-Bach , Adrian Apostol , Laurence Cooke
发明人: Zvi Or-Bach , Adrian Apostol , Laurence Cooke
IPC分类号: H03K19/173
CPC分类号: H03K19/0016 , H03K5/2481 , H03K19/01812 , H04L25/0272
摘要: An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which drive a pair of adjacent wires with differential current pulses that are received by a differential receiver which may be put in a low power state between transmissions.
摘要翻译: 一种半导体器件,包含逻辑块和块之间的高速连接,其中连接利用电流方向进行逻辑表示而不是电压电平。 这种高速连接包括差分发射器,差动发射器用差动接收器接收的差分电流脉冲来驱动一对相邻导线,差动接收器可能在传输之间处于低功率状态。
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公开(公告)号:US07157937B2
公开(公告)日:2007-01-02
申请号:US11186923
申请日:2005-07-22
申请人: Adrian Apostol , Petrica Avram , Romeo Iacobut , Adam Levinthal , Zvi Or-Bach , Ze′ev Wurman , Richard Zeman , Alon Kapel , George C. Grigore
发明人: Adrian Apostol , Petrica Avram , Romeo Iacobut , Adam Levinthal , Zvi Or-Bach , Ze′ev Wurman , Richard Zeman , Alon Kapel , George C. Grigore
IPC分类号: H01L25/00 , H03K19/177
CPC分类号: H03K19/1776 , G01R31/3172 , G01R31/318516 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17796 , H01L2924/00
摘要: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
摘要翻译: 可配置的逻辑阵列可以包括:多个逻辑单元,其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 以及具有可自定义I / O的微处理器,用于配置和测试阵列,其中的定制都在单个通孔层上完成。
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公开(公告)号:US07105871B2
公开(公告)日:2006-09-12
申请号:US10730064
申请日:2003-12-09
申请人: Zvi Or-Bach , Laurence Cooke , Adrian Apostol , Romeo Iacobut
发明人: Zvi Or-Bach , Laurence Cooke , Adrian Apostol , Romeo Iacobut
IPC分类号: H01L27/10
CPC分类号: H01L23/525 , H01L2924/0002 , H01L2924/14 , H01L2924/3011 , H01L2924/00
摘要: A semiconductor device may include a borderless logic array and area I/Os. The logic array may comprise a repeating core, and at least one of the area I/Os may be a configurable I/O. Furthermore, the configurable I/O may comprise at least one metal layer that is the same for all I/O configurations.
摘要翻译: 半导体器件可以包括无边界逻辑阵列和区域I / O。 逻辑阵列可以包括重复核心,并且区域I / O中的至少一个可以是可配置I / O。 此外,可配置I / O可以包括对于所有I / O配置相同的至少一个金属层。
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公开(公告)号:US07550996B2
公开(公告)日:2009-06-23
申请号:US11366528
申请日:2006-03-03
申请人: Zvi Or-Bach , Petrica Avram , Romeo Iacobut , Adrian Apostol , Ze'ev Wurman , Adam Levinthal , Richard Zeman
发明人: Zvi Or-Bach , Petrica Avram , Romeo Iacobut , Adrian Apostol , Ze'ev Wurman , Adam Levinthal , Richard Zeman
IPC分类号: G06F7/38 , H03K19/177
CPC分类号: H03K19/1776 , G01R31/3172 , G01R31/318516 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17796 , H01L2924/00
摘要: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.
摘要翻译: 可配置的逻辑阵列可以包括:多个逻辑单元,其包含查找表; 可定制的金属和覆盖多个逻辑单元的通孔连接层; 多个设备可定制的I / O单元; 多个配置可定制的RAM块; 具有可定制内容的ROM块; 和/或具有可定制I / O的微处理器,可用于配置和测试阵列,其中定制全部在单个通孔层上完成。
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公开(公告)号:US20060164121A1
公开(公告)日:2006-07-27
申请号:US11366528
申请日:2006-03-03
申请人: Zvi Or-Bach , Petrica Avram , Romeo Iacobut , Adrian Apostol , Ze'ev Wurman , Adam Levinthal , Richard Zeman
发明人: Zvi Or-Bach , Petrica Avram , Romeo Iacobut , Adrian Apostol , Ze'ev Wurman , Adam Levinthal , Richard Zeman
IPC分类号: H03K19/177
CPC分类号: H03K19/1776 , G01R31/3172 , G01R31/318516 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17796 , H01L2924/00
摘要: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and/or a microprocessor with customizable I/O, which may be used for configuring and testing the array, where the customizations are all done on a single via layer.
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公开(公告)号:US20060028241A1
公开(公告)日:2006-02-09
申请号:US11186923
申请日:2005-07-22
申请人: Adrian Apostol , Petrica Avram , Romeo Iacobut , Adam Levinthal , Zvi Or-Bach , Ze'ev Wurman , Richard Zeman , Alon Kapel , George Grigore
发明人: Adrian Apostol , Petrica Avram , Romeo Iacobut , Adam Levinthal , Zvi Or-Bach , Ze'ev Wurman , Richard Zeman , Alon Kapel , George Grigore
IPC分类号: H03K19/177
CPC分类号: H03K19/1776 , G01R31/3172 , G01R31/318516 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17796 , H01L2924/00
摘要: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
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公开(公告)号:US20060022705A1
公开(公告)日:2006-02-02
申请号:US10899020
申请日:2004-07-27
申请人: Zvi Or-Bach , Petrica Avram , Romeo Iacobut , Adrian Apostol , Ze'ev Wurman , Adam Leventhal , Richard Zeman
发明人: Zvi Or-Bach , Petrica Avram , Romeo Iacobut , Adrian Apostol , Ze'ev Wurman , Adam Leventhal , Richard Zeman
IPC分类号: H03K19/177
CPC分类号: H03K19/1776 , G01R31/3172 , G01R31/318516 , H01L24/06 , H01L2224/05554 , H01L2924/14 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17796 , H01L2924/00
摘要: A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.
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