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公开(公告)号：US20110121404A1
公开(公告)日：2011-05-26
申请号：US12895813
申请日：2010-09-30
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1083 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L27/088 , H01L27/092 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7836
摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。
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公开(公告)号：US20130181298A1
公开(公告)日：2013-07-18
申请号：US13787073
申请日：2013-03-06
申请人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang , Scott E. Thompson
发明人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang , Scott E. Thompson
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L29/1083 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L27/088 , H01L27/092 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7836
摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。
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公开(公告)号：US08421162B2
公开(公告)日：2013-04-16
申请号：US12895813
申请日：2010-09-30
申请人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang , Scott E. Thompson
发明人： Lucian Shifren , Pushkar Ranade , Paul E. Gregory , Sachin R. Sonkusale , Weimin Zhang , Scott E. Thompson
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/1083 , H01L21/823412 , H01L21/82345 , H01L21/823493 , H01L27/088 , H01L27/092 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/36 , H01L29/66537 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7836
摘要： An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5×1018 dopant atoms per cm3. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.
摘要翻译： 具有穿通抑制的高级晶体管包括具有长度为Lg的阱，阱掺杂以具有掺杂剂的第一浓度，以及位于栅极下方并具有第二掺杂浓度的屏蔽区域。 掺杂剂的第二浓度可以大于每立方厘米5×1018个掺杂剂原子。 在筛选区域和井之间的栅极下方设置有至少一个穿孔抑制区域。 穿通抑制区域具有在第一浓度和第二浓度掺杂剂之间的掺杂剂的第三浓度。 可以将偏置电压施加到阱区域以调整晶体管的阈值电压。
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4.发明授权公开(公告)号：US08530286B2
公开(公告)日：2013-09-10
申请号：US12971884
申请日：2010-12-17
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L29/7833
摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
摘要翻译： 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有降低的sigmaVT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT被设置 更准确地说 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 半导体结构包括模拟器件和数字器件，每个器件和数字器件均具有外延沟道层，其中单个栅极氧化层位于数字器件的NMOS和PMOS晶体管元件的外延沟道层上，并且双栅极和三栅极氧化层之一是 在模拟器件的NMOS和PMOS晶体管元件的外延沟道层上。
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5.发明申请公开(公告)号：US20110248352A1
公开(公告)日：2011-10-13
申请号：US12971884
申请日：2010-12-17
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L29/7833
摘要： A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.
摘要翻译： 其制造的结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT 更精确地设置。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 半导体结构包括模拟器件和数字器件，每个器件和数字器件均具有外延沟道层，其中单个栅极氧化层位于数字器件的NMOS和PMOS晶体管元件的外延沟道层上，并且双栅极和三栅极氧化层之一是 在模拟器件的NMOS和PMOS晶体管元件的外延沟道层上。
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公开(公告)号：US08569128B2
公开(公告)日：2013-10-29
申请号：US12960266
申请日：2010-12-03
IPC分类号： H01L21/823842 , H01L21/823807
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823842 , H01L27/0922
摘要： A semiconductor structure includes a first PMOS transistor element having a gate region with a first gate metal associated with a PMOS work function and a first NMOS transistor element having a gate region with a second metal associated with a NMOS work function. The first PMOS transistor element and the first NMOS transistor element form a first CMOS device. The semiconductor structure also includes a second PMOS transistor that is formed in part by concurrent deposition with the first NMOS transistor element of the second metal associated with a NMOS work function to form a second CMOS device with different operating characteristics than the first CMOS device.
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公开(公告)号：US08563384B2
公开(公告)日：2013-10-22
申请号：US13770313
申请日：2013-02-19
IPC分类号： H01L21/336 , H01L21/70 , H01L29/02
CPC分类号： H01L29/7816 , H01L27/085 , H01L27/088 , H01L29/105 , H01L29/1083 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7835 , H01L29/7848
摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
摘要翻译： 具有改进性能的平面晶体管在半导体衬底上具有源极和漏极，其包括在源极和漏极之间延伸的基本上未掺杂的沟道。 栅极位于衬底上的基本上未掺杂的沟道上。 注入源极/漏极延伸部接触源极和漏极，注入源极/漏极延伸部的掺杂剂浓度小于约1×1019原子/ cm3'，或者可选地，小于源极的掺杂剂浓度的四分之一，以及 排水。
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公开(公告)号：US08404551B2
公开(公告)日：2013-03-26
申请号：US12960289
申请日：2010-12-03
IPC分类号： H01L21/336 , H01L21/70 , H01L29/02
CPC分类号： H01L29/7816 , H01L27/085 , H01L27/088 , H01L29/105 , H01L29/1083 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7835 , H01L29/7848
摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
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公开(公告)号：US20130161743A1
公开(公告)日：2013-06-27
申请号：US13770313
申请日：2013-02-19
IPC分类号： H01L29/78 , H01L27/085
CPC分类号： H01L29/7816 , H01L27/085 , H01L27/088 , H01L29/105 , H01L29/1083 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7835 , H01L29/7848
摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
摘要翻译： 具有改进性能的平面晶体管在半导体衬底上具有源极和漏极，其包括在源极和漏极之间延伸的基本上未掺杂的沟道。 栅极位于衬底上的基本上未掺杂的沟道上。 注入源极/漏极延伸部接触源极和漏极，注入源极/漏极延伸部的掺杂剂浓度小于约1×1019原子/ cm3'，或者可选地，小于源极的掺杂剂浓度的四分之一，以及 排水。
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公开(公告)号：US20120139051A1
公开(公告)日：2012-06-07
申请号：US12960289
申请日：2010-12-03
IPC分类号： H01L21/336 , H01L29/10
CPC分类号： H01L29/7816 , H01L27/085 , H01L27/088 , H01L29/105 , H01L29/1083 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7835 , H01L29/7848
摘要： A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
摘要翻译： 具有改进性能的平面晶体管在半导体衬底上具有源极和漏极，其包括在源极和漏极之间延伸的基本上未掺杂的沟道。 栅极位于衬底上的基本上未掺杂的沟道上。 注入源极/漏极延伸部接触源极和漏极，注入源极/漏极延伸部的掺杂剂浓度小于约1×1019原子/ cm3，或者可选地，小于源极的掺杂剂浓度的四分之一 排水。
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