公开(公告)号：US5160862A

公开(公告)日：1992-11-03

申请号：US788594

申请日：1991-11-06

申请人： Ludwig Leipold ,  Hubert Rothleitner ,  Rainald Sander ,  Jenoe Tihanyi

发明人： Ludwig Leipold ,  Hubert Rothleitner ,  Rainald Sander ,  Jenoe Tihanyi

IPC分类号： H03K17/06 ,  H03K17/082 ,  H03K17/16 ,  H03K17/687 ,  H03K17/695

CPC分类号： H03K17/0822 ,  H03K17/063 ,  H03K17/6877

摘要： In order to rapidly reduce the magnetic energy of an inductive load (2), the driving voltage must be high. When the load (2) is disconnected via a MOSFET (3), then a premature activation of the MOSFET (3) given reversal of the voltage at the inductive load (2) must be prevented. A series circuit of a Zener diode and of a controllable switch (3) is connected between the gate and the load (2). A current source (depletion MOSFET 5) whose current is lower than the current that would flow upon Zener breakdown is connected between the gate and the source of the power MOSFET (1). The MOSFET (3) becomes conductive upon Zener breakdown and the energy is quickly reduced by a high voltage, essentially by the Zener voltage.

摘要翻译： 为了快速降低感性负载（2）的磁能，驱动电压必须很高。 当负载（2）通过MOSFET（3）断开时，必须防止给定电感负载（2）电压反转的MOSFET（3）过早启动。 齐纳二极管和可控开关（3）的串联电路连接在栅极和负载（2）之间。 电流低于齐纳击穿时流过的电流的电流源（耗尽型MOSFET5）连接在功率MOSFET（1）的栅极和源极之间。 基于齐纳电压，MOSFET（3）在齐纳击穿时变为导通，并且能量通过高电压快速降低。

公开(公告)号：US5434521A

公开(公告)日：1995-07-18

申请号：US978637

申请日：1992-11-19

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi

IPC分类号： G01R19/165 ,  H03K5/08 ,  H03K17/30 ,  H03K17/687 ,  H03K5/153

CPC分类号： H03K17/6872 ,  G01R19/16519 ,  H03K17/302

摘要： An integrated comparator circuit includes two complementary MOSFETs having main current paths being connected together in a series circuit at a connecting point. An inverter stage has two complementary MOSFETs with gate terminals connected to the connecting point. First, second and third terminals are provided. The first and second terminals are for an operating voltage, and the second and third terminals are for a voltage to be compared. The series circuit is connected between the first and third terminals, and the inverter stage is connected between the first and second terminals. One of the MOSFETs of the series circuit connected to the first terminal and one of the MOSFETs of the inverter stage connected to the first terminal are of the same channel type. The other of the MOSFETs of the series circuit connected to the third terminal and the other of the MOSFETs of the inverter stage connected the second terminal are of the same channel type.

摘要翻译： 集成比较器电路包括两个互补MOSFET，其中主电流路径在连接点处串联在一起连接在一起。 反相器级具有两个互补MOSFET，栅极端子连接到连接点。 首先，提供第二和第三终端。 第一和第二端子用于工作电压，第二和第三端子用于比较电压。 串联电路连接在第一和第三端子之间，变频器级连接在第一和第二端子之间。 连接到第一端子的串联电路的MOSFET之一和连接到第一端子的反相器级的MOSFET之一具有相同的通道类型。 连接到第三端子的串联电路的另一个MOSFET和连接到第二端子的反相器级的另一个MOSFET具有相同的通道类型。

公开(公告)号：US5371418A

公开(公告)日：1994-12-06

申请号：US95197

申请日：1993-07-23

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi

IPC分类号： H01L27/088 ,  H03K17/00 ,  H03K17/06 ,  H03K17/687

CPC分类号： H03K17/6877 ,  H01L27/0883 ,  H03K17/063 ,  H03K2217/0036

摘要： Power FETs having a load at the source side require a gate voltage lying above the drain voltage in order to be driven completely conductive. This can occur with a known pump circuit. In the drive circuit disclosed, the diode connected to the gate terminal of the power FET is a depletion FET whose substrate terminal is applied to the oscillating voltage that is required for the operation of the pump circuit. The cut off voltage is thus synchronously set relative to the oscillating voltage such that low losses arise when loading C.sub.GS and an adequately high inhibit voltage can be built up when loading the pump capacitor.

摘要翻译： 在源极处具有负载的功率FET需要位于漏极电压之上的栅极电压，以便被驱动完全导电。 这可以用已知的泵电路进行。 在所公开的驱动电路中，连接到功率FET的栅极端子的二极管是耗尽FET，其基极端子被施加到泵电路的操作所需的振荡电压。 因此，截止电压相对于振荡电压被同步设定，使得当加载CGS时产生低损耗，并且当加载泵电容器时可以建立足够高的抑制电压。

公开(公告)号：US5272399A

公开(公告)日：1993-12-21

申请号：US4970

申请日：1993-01-15

申请人： Jenoe Tihanyi ,  Ludwig Leipold ,  Rainald Sander

发明人： Jenoe Tihanyi ,  Ludwig Leipold ,  Rainald Sander

IPC分类号： H02H7/20 ,  H03K17/08 ,  H03K17/082 ,  H03K3/01 ,  H03K5/08

CPC分类号： H03K17/0822

摘要： A circuit configuration for limiting current flowing through a power MOSFET includes a voltage divider being connected between drain and source terminals of the power MOSFET and having a node at which a voltage following a drain-to-source voltage of the power MOSFET drops. A control transistor has a load path connected between the gate terminal and the source terminal of the power MOSFET. The control transistor is made conducting as a function of the voltage at the node of the voltage divider if the drain-to-source voltage of the power MOSFET exceeds a predetermined value. A resistor is connected between the gate terminal of the control transistor and the gate terminal of the power MOSFET. A depletion FET has a drain terminal connected to the gate terminal of the control transistor. The source terminal of the depletion FET is connected to the node of the voltage divider. The gate terminal of the depletion FET is connected to the source terminal of the power MOSFET.

摘要翻译： 用于限制流过功率MOSFET的电流的电路配置包括分压器，其连接在功率MOSFET的漏极和源极端子之间，并且具有在功率MOSFET的漏极 - 源极电压之后的电压下降的节点。 控制晶体管具有连接在功率MOSFET的栅极端子和源极端子之间的负载路径。 如果功率MOSFET的漏极 - 源极电压超过预定值，则控制晶体管作为分压器节点处的电压的函数导通。 电阻连接在控制晶体管的栅极端子和功率MOSFET的栅极端子之间。 耗尽FET具有连接到控制晶体管的栅极端子的漏极端子。 耗尽FET的源极端子连接到分压器的节点。 耗尽FET的栅极端子连接到功率MOSFET的源极端子。

公开(公告)号：US5086364A

公开(公告)日：1992-02-04

申请号：US657291

申请日：1991-02-19

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber

IPC分类号： G01R31/02 ,  H03K17/082

CPC分类号： H03K17/0822 ,  G01R31/025

摘要： The voltage (U.sub.DS) on a power MOSFET (1) is compared with a voltage (U.sub.V) derived from the sum of the voltages of a Zener diode (3) and the threshold voltage (U.sub.T) of a second MOSFET (5) to detect a short circuit in a load (2) in series with the power MOSFET (1). When this total voltage is exceeded, the second MOSFET conducts. Its load current is then evaluated as the short circuit signal.

摘要翻译： 功率MOSFET（1）上的电压（UDS）与从齐纳二极管（3）的电压和第二MOSFET（5）的阈值电压（UT）之和导出的电压（UV）进行比较，以检测 与功率MOSFET（1）串联的负载（2）中的短路。 当超过该总电压时，第二个MOSFET导通。 然后将其负载电流评估为短路信号。

公开(公告)号：US5726478A

公开(公告)日：1998-03-10

申请号：US769348

申请日：1996-12-19

申请人： Josef-Matthias Gantioler ,  Ludwig Leipold ,  Rainald Sander ,  Jens-Peer Stengl ,  Jenoe Tihanyi

发明人： Josef-Matthias Gantioler ,  Ludwig Leipold ,  Rainald Sander ,  Jens-Peer Stengl ,  Jenoe Tihanyi

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L23/62

CPC分类号： H01L27/0251 ,  H01L2924/0002

摘要： An integrated power semiconductor component includes a substrate of a first conduction type. At least one first region of a second conduction type is embedded in the substrate and at least one second region of the second conduction type is embedded in the substrate. A substrate contact supplies a supply voltage. Contact-making semiconductor components are embedded in the first region and in the second region. At least a portion of the semiconductor components in the first region control at least a portion of the semiconductor components in the second region. A third region of the second conduction type is disposed between the first region and the second region, and the first region and the third region are at different potentials.

摘要翻译： 集成功率半导体元件包括第一导电类型的衬底。 至少一个第二导电类型的第一区域被嵌入衬底中，并且第二导电类型的至少一个第二区域被嵌入衬底中。 基板触点提供电源电压。 接触半导体部件嵌入在第一区域和第二区域中。 第一区域中的半导体部件的至少一部分控制第二区域中的至少一部分半导体部件。 第二导电类型的第三区域设置在第一区域和第二区域之间，并且第一区域和第三区域处于不同的电位。

公开(公告)号：US5266840A

公开(公告)日：1993-11-30

申请号：US999687

申请日：1992-12-31

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber

IPC分类号： B60Q11/00 ,  G01R31/02 ,  H05B37/03 ,  H01J1/00

CPC分类号： H05B37/03 ,  B60Q11/005 ,  G01R31/024 ,  Y10T307/826

摘要： A circuit for detecting the non-operating condition of a load which is connected in series with an electronic switch wherein a comparator has a first input which is connected to the junction point between the load and the electronic switch and has a second input which is a reference voltage such that when the load fails the comparator produces an output to indicate such condition and wherein the reference voltage is lower than the normal voltage when the load is operating properly and is higher than when the load is in the inoperative condition.

摘要翻译： 一种用于检测与电子开关串联连接的负载的非工作状态的电路，其中比较器具有连接到负载和电子开关之间的连接点的第一输入端，并且具有第二输入端 参考电压使得当负载故障时，比较器产生用于指示这种状况的输出，并且其中当负载正常工作时，参考电压低于正常电压，并且高于负载处于不工作状态时的参考电压。

公开(公告)号：US4952827A

公开(公告)日：1990-08-28

申请号：US438342

申请日：1989-11-15

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber ,  Nance: Paul

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber ,  Nance: Paul

IPC分类号： H03K17/08 ,  H03K17/06 ,  H03K17/082

CPC分类号： H03K17/0822 ,  H03K17/063

摘要： A circuit arrangement for controlling load current of a power MOSFET wherein the load is connected at the source terminal includes a second FET having a defined threshold voltage connected with its drain-source path inserted between the gate and source of the power MOSFET. A third FET connects the gate terminal of the second FET to the drain voltage of the power MOSFET when the power MOSFET is in the conductive condition. When the drain-source voltage of the power MOSFET becomes higher than the threshold voltage of the second FET, the second FET becomes conductive and drives the gate-source voltage of the power MOSFET down.

摘要翻译： 用于控制功率MOSFET的负载电流的电路装置，其中负载在源极端子处连接包括具有限定的阈值电压的第二FET，该阈值电压与插入在功率MOSFET的栅极和源极之间的漏极 - 源极路径连接。 当功率MOSFET处于导通状态时，第三FET将第二FET的栅极端子连接到功率MOSFET的漏极电压。 当功率MOSFET的漏源电压变得高于第二FET的阈值电压时，第二FET变为导通状态，并将功率MOSFET的栅极 - 源极电压降低。

公开(公告)号：US5172290A

公开(公告)日：1992-12-15

申请号：US382523

申请日：1989-07-20

申请人： Ludwig Leipold ,  Jenoe Tihanyi ,  Roland Weber ,  Rainald Sander

发明人： Ludwig Leipold ,  Jenoe Tihanyi ,  Roland Weber ,  Rainald Sander

IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/04 ,  H03K17/0812

CPC分类号： H03K17/08122 ,  H01L27/0251

摘要： The gate-source capacitance of a power MOSFET (1) can be protected against positive and negative excess voltages by two integrated Zener diodes (3, 4) the anodes of which are coupled to each other and the cathodes of which are respectively coupled to the gate and source terminals of the power MOSFET. However, when a control voltage is applied, the parasitic bipolar transistor associated with one of the Zener diodes is switched on and prevents the MOSFET from completely switching on. The parasitic bipolar transistor is rendered harmless by the fact that the anode terminal is coupled to a source terminal (S) MOSFET (1) when a gate-source voltage is applied.

摘要翻译： 功率MOSFET（1）的栅极 - 源极电容可以通过两个集成的齐纳二极管（3,4）被保护，以防止正和负的过剩电压，它们的阳极彼此耦合，并且阴极分别耦合到 功率MOSFET的栅极和源极端子。 然而，当施加控制电压时，与齐纳二极管之一相关联的寄生双极晶体管导通，并防止MOSFET完全导通。 当施加栅极 - 源极电压时，寄生双极晶体管由于阳极端子耦合到源极端子（S）MOSFET（1）的事实而变得无害。

公开(公告)号：US4875131A

公开(公告)日：1989-10-17

申请号：US342835

申请日：1989-04-25

申请人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber

发明人： Ludwig Leipold ,  Rainald Sander ,  Jenoe Tihanyi ,  Roland Weber

IPC分类号： H01L23/58 ,  G01K7/01 ,  G05F1/10 ,  H01L21/8222 ,  H01L27/06 ,  H02H5/04 ,  H03K17/08 ,  H03K17/14

CPC分类号： H02H5/044 ,  G01K7/01 ,  H01L2924/0002

摘要： A circuit for monitoring the temperature of a semiconductor structural component. The circuit includes a bipolar transistor (1) in thermal contact with a semiconductor structural element to be monitored, and a MOSFET (11) connected in series with a current source (12). The MOSFET (11) is maintained in a nonconducting state with two Zener diodes (13, 14) if the bipolar transistor (1) is the standard operating temperature of the semiconductor structural element. This circuit provides for a reduced zero current signal. The current flowing through the bipolar transistor (1) increases with temperature and the gate-source voltage of the MOSFET (11) is increases until it switches off. If the current flowing through the MOSFET (11) is greater than the impressed current of the current source (12) the potential across the current source takes a step increase a value near the supply voltage (V.sub.DD). This voltage step can then be detected as an excess-temperature signal.

摘要翻译： 一种用于监测半导体结构部件的温度的电路。 电路包括与待监控的半导体结构元件热接触的双极晶体管（1）和与电流源（12）串联连接的MOSFET（11）。 如果双极晶体管（1）是半导体结构元件的标准工作温度，则MOSFET（11）保持在具有两个齐纳二极管（13,14）的非导通状态。 该电路提供减少的零电流信号。 流过双极晶体管（1）的电流随着温度而升高，并且MOSFET（11）的栅极 - 源极电压增加直至其断开。 如果流过MOSFET（11）的电流大于电流源（12）的外加电流，电流源两端的电位会在电源电压（VDD）附近逐步增加一个值。 然后可以将该电压步骤检测为过温信号。