公开(公告)号：US20210081274A1

公开(公告)日：2021-03-18

申请号：US16571260

申请日：2019-09-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Ping-Hsien LIN ,  Kun-Chi CHIANG ,  Chien-Chung HO

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G11C11/409 ,  G11C11/4074

Abstract: A memory data management method includes the following steps: reading a plurality of data of a plurality of memory cells of a memory block; determining whether error bits of the data exceed an error correction code (ECC) threshold; if the error bits of the data exceed the ECC threshold, a programming process being executed to enhance a first state data of the data for exceeding a first threshold, to enhance a second state data of the data for exceeding a second threshold, and to enhance a third state data of the data for exceeding a third threshold.

公开(公告)号：US20200319998A1

公开(公告)日：2020-10-08

申请号：US16655510

申请日：2019-10-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Hung-Sheng CHANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F12/02 ,  G06N3/08 ,  G06N3/10 ,  G11C7/10

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

公开(公告)号：US20230221956A1

公开(公告)日：2023-07-13

申请号：US17830453

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Huai-Mu WANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F9/30 ,  G06F7/544 ,  G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

CPC classification number: G06F9/3004 ,  G06F9/30036 ,  G06F9/3001 ,  G06F7/5443 ,  G11C16/3404 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US20230221882A1

公开(公告)日：2023-07-13

申请号：US17830471

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Huai-Mu WANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US20200319808A1

公开(公告)日：2020-10-08

申请号：US16564066

申请日：2019-09-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Hung-Sheng CHANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06 ,  G06N3/04

Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.