公开(公告)号：US20200319998A1

公开(公告)日：2020-10-08

申请号：US16655510

申请日：2019-10-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Hung-Sheng CHANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F12/02 ,  G06N3/08 ,  G06N3/10 ,  G11C7/10

Abstract: A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.

公开(公告)号：US20210081140A1

公开(公告)日：2021-03-18

申请号：US16571249

申请日：2019-09-16

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ping-Hsien LIN ,  Wei-Chen WANG ,  Hsiang-Pang LI ,  Shu-Hsien LIAO ,  Che-Wei TSAO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06 ,  G11C16/10

Abstract: The present disclosure provides a memory system, a method of operating memory, and a non-transitory computer readable storage medium. The memory system includes a memory chip and a controller. The controller is coupled with the memory chip, which the controller is configured to: receive a first data corresponding to a first version from a file system in order to store the first data corresponding to the first version in a first page of the flash memory chip; and program the first data corresponding to a second version in the first page in response to the first data of the second version, which the second version is newer than the first version.

公开(公告)号：US20240036735A1

公开(公告)日：2024-02-01

申请号：US17814888

申请日：2022-07-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Tse-Yuan WANG ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0679 ,  G06F3/0644

Abstract: An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

公开(公告)号：US20220155959A1

公开(公告)日：2022-05-19

申请号：US17518624

申请日：2021-11-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Ting-Hsuan LO ,  Chun-Feng WU ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06

Abstract: Disclosed is a memory device and an operation method thereof. The operation method of memory device, comprising: programming a plurality of sub-matrices including at least one of non-zero element of a rearranged matrix to a plurality of operation units of the memory device; and programming a mapping table into a working memory of a memory device. The rearranged matrix is generated by rearrange a plurality of columns and a plurality of rows of an original matrix according to the positions of a plurality of non-zero elements of the original matrix. The mapping table comprises a correspondence of row indexes between the original matrix and the rearranged matrix, a correspondence of column indexes between the original matrix and the rearranged matrix and a correspondence between the sub-matrices including at least one non-zero element and the operation units storing the sub-matrices including at least one non-zero element.

公开(公告)号：US20230221956A1

公开(公告)日：2023-07-13

申请号：US17830453

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Huai-Mu WANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F9/30 ,  G06F7/544 ,  G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

CPC classification number: G06F9/3004 ,  G06F9/30036 ,  G06F9/3001 ,  G06F7/5443 ,  G11C16/3404 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. Each vector data is executed with a multiplying-operation, the MSB vector and the LSB vector of each vector data is executed with a first group-counting operation and a second group-counting operation respectively. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US20230221882A1

公开(公告)日：2023-07-13

申请号：US17830471

申请日：2022-06-02

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Han-Wen HU ,  Yung-Chun LI ,  Huai-Mu WANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

公开(公告)号：US20200319808A1

公开(公告)日：2020-10-08

申请号：US16564066

申请日：2019-09-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Hung-Sheng CHANG ,  Chien-Chung HO ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06F3/06 ,  G06N3/04

Abstract: A memory device includes: a memory array used for implementing neural networks (NN), the NN including a plurality of layers; and a controller coupled to the memory array, the controller being configured for: determining a computation duration of a first data of a first layer of the plurality of layers; selecting a first program operation if the computation duration of the first data of the first layer is shorter than a threshold; and selecting a second program operation if the computation duration of the first data of the first layer is longer than the threshold, wherein the second program operation has a longer program pulse time than the first program operation.

公开(公告)号：US20230162024A1

公开(公告)日：2023-05-25

申请号：US17686478

申请日：2022-03-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen WANG ,  Yu-Pang WANG ,  Yuan-Hao CHANG ,  Tei-Wei KUO

IPC: G06N3/08 ,  G06F7/544

CPC classification number: G06N3/08 ,  G06F7/5443

Abstract: A Ternary Content Addressable Memory (TCAM)-based training method for graph neural network and a memory device using the same are provided. The TCAM-based training method for Graph Neural Network includes the following steps. Data are sampled from a dataset. The Graph Neural Network is trained according to the data from the dataset. The step of training the Graph Neural Network includes a feature extraction phase, an aggregation phase and an update phase. In the aggregation phase, one TCAM crossbar matrix stores a plurality of edges corresponding to one vertex and outputs a hit vector for selecting some of the edges, and a Multiply Accumulate (MAC) crossbar matrix stores a plurality of features in the edges for performing a multiply accumulate operation according to the hit vector.

公开(公告)号：US20210375357A1

公开(公告)日：2021-12-02

申请号：US17035885

申请日：2020-09-29

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Chun LI ,  Wei-Chen WANG

IPC: G11C11/56 ,  G11C16/10 ,  G06F12/02

Abstract: A data management method for a memory is provided. The memory includes memory pages. Each of the memory pages includes memory cells. A data update command corresponding to a logical address is received. The logical address maps to a physical address of a target memory page before receiving the data update command. First and second reading voltages are applied to obtain at least a first and a second target memory cell to be sanitized in the target memory page of the memory pages, a first programming voltage is applied to change the logical state of the first target memory cell to a logical state with a higher threshold voltage, and a second programming voltage is applied to change the logical state of the second target memory cell to a logical state with a higher threshold voltage. The first programming voltage is different from the second programming voltage.