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公开(公告)号：US20240030938A1
公开(公告)日：2024-01-25
申请号：US17868251
申请日：2022-07-19
Applicant: MACRONIX International Co., Ltd.
Inventor： Kuan-Chieh Wang
CPC classification number: H03M13/1108 , H03M13/159 , G06F7/501 , H03M13/112
Abstract: A memory device, an error correction device and an error correction method thereof are provided. The error correction device includes a first error correction decoder and a second error correction decoder. The first error correction decoder performs at least one iteration of a first error correction operation on a data chunk, calculates a counting number of syndrome values equal to a set logic value generated in the at least one iteration of the first error correction operation, and generates a control signal according to the counting number. The second error correction decoder receives the control signal and determines whether to be activated to perform a second error correction operation on the data chunk or not according to the control signal. An error correction ability of the second error correction decoder is higher than an error correction ability of the first error correction decoder.
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公开(公告)号：US20230026403A1
公开(公告)日：2023-01-26
申请号：US17957597
申请日：2022-09-30
Applicant: Macronix International Co., Ltd.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan
Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.
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Patent Agency Ranking
公开(公告)号：US11983124B2
公开(公告)日：2024-05-14
申请号：US17957597
申请日：2022-09-30
Applicant: Macronix International Co., Ltd.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan
CPC classification number: G06F13/1668 , G06F11/1076 , H03M13/45
Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.
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公开(公告)号：US11949429B2
公开(公告)日：2024-04-02
申请号：US17868251
申请日：2022-07-19
Applicant: MACRONIX International Co., Ltd.
Inventor： Kuan-Chieh Wang
CPC classification number: H03M13/1108 , G06F7/501 , H03M13/112 , H03M13/159
Abstract: A memory device, an error correction device and an error correction method thereof are provided. The error correction device includes a first error correction decoder and a second error correction decoder. The first error correction decoder performs at least one iteration of a first error correction operation on a data chunk, calculates a counting number of syndrome values equal to a set logic value generated in the at least one iteration of the first error correction operation, and generates a control signal according to the counting number. The second error correction decoder receives the control signal and determines whether to be activated to perform a second error correction operation on the data chunk or not according to the control signal. An error correction ability of the second error correction decoder is higher than an error correction ability of the first error correction decoder.
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公开(公告)号：US11809746B2
公开(公告)日：2023-11-07
申请号：US17541306
申请日：2021-12-03
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan , Nai-Ping Kuo
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0626 , G06F3/0656 , G06F3/0679
Abstract: A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.
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公开(公告)号：US11556420B2
公开(公告)日：2023-01-17
申请号：US17223545
申请日：2021-04-06
Applicant: Macronix International Co., Ltd.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan
Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.
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公开(公告)号：US20220318090A1
公开(公告)日：2022-10-06
申请号：US17223545
申请日：2021-04-06
Applicant: Macronix International Co., Ltd.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan
Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.
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