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公开(公告)号：US11327907B2
公开(公告)日：2022-05-10
申请号：US16923336
申请日：2020-07-08
Applicant: Macronix International Co., Ltd.
Inventor： Shunli Cheng , Shih-Chou Juan
Abstract: Method and apparatus for improving continuous read operations with expanded serial interface are provided. In one aspect, a device comprises: a memory configured to store data; a buffer configured to receive data from outside of the device and transfer the received data to the memory; a plurality of input pins configured to be coupled to an expanded serial peripheral interface (xSPI); and a processor configured to: select a slave device, through the xSPI, from a plurality of slave devices, send instruction data to the slave device for data reading, receive data, through the xSPI, from the selected slave device, and receive a signal on a data strobe line of the xSPI and determine data reading operations based on the received signal.
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公开(公告)号：US12197749B2
公开(公告)日：2025-01-14
申请号：US17940446
申请日：2022-09-08
Applicant: Macronix International Co., Ltd.
Inventor： Shun-Li Cheng , Shih-Chou Juan
Abstract: Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, a system includes a semiconductor device configured to store data, and a controller communicatively coupled to the semiconductor device. The controller is configured to send, to the semiconductor device, an instruction requesting transmission of the data; in response to determining that a predetermined time duration has elapsed after sending the instruction, initiate transmission of a read enable signal to the semiconductor device; receive, from the semiconductor device, a data strobe signal; and, in response to determining that the data strobe signal has a frequency matching a frequency of the read enable signal, read the data from the semiconductor device.
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公开(公告)号：US12067267B2
公开(公告)日：2024-08-20
申请号：US18082932
申请日：2022-12-16
Applicant: Macronix International Co., Ltd.
Inventor： Shih-Chou Juan , Wei-Yan Jang
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0653 , G06F3/0679
Abstract: A system includes a semiconductor device configured to store data and a controller communicatively coupled to the semiconductor device. The semiconductor device and the controller are configured to; in response to determining that particular data stored in the semiconductor device satisfies a reliability condition, obtain first readout data by reading the particular data at a first read voltage, and obtain second readout data by reading the particular data at a second read voltage. The second read voltage is different from the first read voltage. The semiconductor device and the controller are configured to compare the first readout data and the second readout data and obtain a comparison result; and, based on the comparison result, determine whether to perform an error correction process on the particular data.
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公开(公告)号：US11983124B2
公开(公告)日：2024-05-14
申请号：US17957597
申请日：2022-09-30
Applicant: Macronix International Co., Ltd.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan
CPC classification number: G06F13/1668 , G06F11/1076 , H03M13/45
Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.
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公开(公告)号：US20240086087A1
公开(公告)日：2024-03-14
申请号：US17940446
申请日：2022-09-08
Applicant: Macronix International Co., Ltd.
Inventor： Shun-Li Cheng , Shih-Chou Juan
CPC classification number: G06F3/0625 , G06F3/0659 , G06F3/0679 , G11C16/32
Abstract: Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, a system includes a semiconductor device configured to store data, and a controller communicatively coupled to the semiconductor device. The controller is configured to send, to the semiconductor device, an instruction requesting transmission of the data; in response to determining that a predetermined time duration has elapsed after sending the instruction, initiate transmission of a read enable signal to the semiconductor device; receive, from the semiconductor device, a data strobe signal; and, in response to determining that the data strobe signal has a frequency matching a frequency of the read enable signal, read the data from the semiconductor device.
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Patent Agency Ranking
公开(公告)号：US20140269074A1
公开(公告)日：2014-09-18
申请号：US13950942
申请日：2013-07-25
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Lung Yi KUO , Hsin Yi Ho , Chun Hsiung Hung , Shuo-Nan Hung , Han-Sung Chen , Shih-Chou Juan
CPC classification number: G11C16/10 , G11C29/808 , G11C29/82 , G11C2029/4402
Abstract: A method for programming a non-volatile memory including a plurality of blocks, each block including a plurality of sections, each section including at least one page, and each page including a plurality of memory cells. The method includes checking a current section of the plurality of sections against a damaged section table to determine whether the current section is damaged. The damaged section table records information about whether a section in the memory is good or damaged. The method further includes using the current section for programming if the current section is not damaged.
Abstract translation: 一种用于编程包括多个块的非易失性存储器的方法，每个块包括多个部分，每个部分包括至少一个页面，并且每个页面包括多个存储器单元。 该方法包括根据损坏部分表检查多个部分的当前部分，以确定当前部分是否损坏。 损坏的部分表记录有关内存中的部分是好还是损坏的信息。 该方法还包括如果当前部分没有损坏，则使用当前部分进行编程。
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公开(公告)号：US20240111453A1
公开(公告)日：2024-04-04
申请号：US17955555
申请日：2022-09-29
Applicant: MACRONIX International Co., Ltd.
Inventor： Jia-Xing Lin , Nai-Ping Kuo , Shih-Chou Juan , Chien-Hsin Liu , Shunli Cheng
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.
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公开(公告)号：US11809746B2
公开(公告)日：2023-11-07
申请号：US17541306
申请日：2021-12-03
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan , Nai-Ping Kuo
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0626 , G06F3/0656 , G06F3/0679
Abstract: A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.
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公开(公告)号：US11556420B2
公开(公告)日：2023-01-17
申请号：US17223545
申请日：2021-04-06
Applicant: Macronix International Co., Ltd.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan
Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.
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公开(公告)号：US20220318090A1
公开(公告)日：2022-10-06
申请号：US17223545
申请日：2021-04-06
Applicant: Macronix International Co., Ltd.
Inventor： Kuan-Chieh Wang , Shih-Chou Juan
Abstract: Methods, devices, systems, and apparatus including computer-readable mediums for managing error correction coding in memory systems are provided. In one aspect, a memory system includes a system controller configured to communicate with a host device, and a memory device coupled to the system controller. The memory device includes at least one memory and a memory controller coupled to the at least one memory. The memory controller includes an error correction code (ECC) circuit configured to perform error correction coding for data received from at least one of the system controller or the at least one memory.
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