公开(公告)号：US09437264B2

公开(公告)日：2016-09-06

申请号：US15055329

申请日：2016-02-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Hsiung Hung ,  Han-Sung Chen ,  Ming-Chao Lin

IPC: G11C8/08 ,  G11C16/30 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2272 ,  G11C2207/2281

Abstract: An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.

Abstract translation: 具有存储器的集成电路可以在诸如读取操作的连续操作之间以较低的延迟进行操作。 第一次，在集成电路上的存储器阵列上完成第一操作命令。 第二次，在存储器阵列上开始第二操作命令。 来自电荷泵的稳定的输出电压被耦合到存储器阵列中的字线。 从第一次到第二次，稳定的输出电压保持在诸如读取电压的字线操作电压。

公开(公告)号：US09679653B2

公开(公告)日：2017-06-13

申请号：US14862064

申请日：2015-09-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Chao Lin ,  Han-Sung Chen

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/3459

Abstract: A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a cell and executing a program and program verify operation for the cell, including applying a sequence of program pulses and performing program verify steps. The sequence includes a starting pulse having a starting magnitude. The program verify steps use a program verify level. The method also comprises determining the starting magnitude for a next cell as a function of a magnitude of the program pulse in an instance of the program verify step in which the current cell passes verify at the program verify level.

公开(公告)号：US09280412B2

公开(公告)日：2016-03-08

申请号：US13890698

申请日：2013-05-09

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wen-Feng Hsueh ,  Ming-Chao Lin

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F11/0793 ,  G06F11/0751 ,  G06F11/1048 ,  G11C2029/0411

Abstract: A non-volatile memory array storing data and ECCs includes error correcting logic. A data set can be read by performing iterations including sensing data using a read bias, and producing an indication of errors in the sensed data. A first iteration uses a first read bias. In each iteration, if the indication in a current iteration is less than a threshold, then the data is output from the selected cells sensed in the present iteration. If the indication in the current iteration exceeds the threshold, then another iteration is performed using a moved read bias, unless the indication in the current iteration shows an increase in errors relative to a previous iteration, in which case then sensed data from the previous iteration is output. Double buffering logic can be used to store sensed data during a current and a previous iteration.

Abstract translation: 存储数据和ECC的非易失性存储器阵列包括纠错逻辑。 可以通过执行迭代来读取数据集，包括使用读取偏差来检测数据，并产生感测数据中的错误的指示。 第一次迭代使用第一个读取偏差。 在每次迭代中，如果当前迭代中的指示小于阈值，则从当前迭代中感测到的所选小区输出数据。 如果当前迭代中的指示超过阈值，则使用移动的读取偏差执行另一次迭代，除非当前迭代中的指示显示相对于先前迭代的错误增加，在这种情况下，然后从上一次迭代中检测数据 被输出。 双缓冲逻辑可用于在当前和之前的迭代期间存储感测数据。

公开(公告)号：US09171628B2

公开(公告)日：2015-10-27

申请号：US14210063

申请日：2014-03-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Ming-Chao Lin ,  Han-Sung Chen

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/3459

Abstract: A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a current cell and executing a pre-program verify operation at a first program verify level. The method comprises executing a program and program verify operation for the current cell, including applying a sequence of program pulses and performing program verify steps. The sequence includes a starting pulse having a starting magnitude. The program verify steps use a second program verify level. The method also comprises determining the starting magnitude for a next cell as a function of a magnitude of the program pulse in an instance of the program verify step in which the current cell passes verify at the second program verify level.

Abstract translation: 提供了一种用于对包括多个存储单元的存储器进行编程的方法。 该方法包括在第一程序验证级别选择当前小区并执行预编程验证操作。 该方法包括对当前小区执行程序和程序验证操作，包括应用程序脉冲序列并执行程序验证步骤。 该序列包括具有起始幅度的起始脉冲。 程序验证步骤使用第二个程序验证级别。 该方法还包括在当前小区在第二程序验证级别通过验证的程序验证步骤的情况下，根据程序脉冲的大小来确定下一个单元的起始幅度。