中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.036 seconds)

    MEMORY DEVICE AND OPERATING METHOD OF SAME
    1.
    发明申请
    MEMORY DEVICE AND OPERATING METHOD OF SAME 有权
    存储器件及其操作方法

    公开(公告)号：US20160299710A1

    公开(公告)日：2016-10-13

    申请号：US14683630

    申请日：2015-04-10

    Applicant: Macronix International Co., Ltd

    Inventor： Yu-Ming CHANG ,  Wei-Chieh HUANG ,  Li-Chun HUANG ,  Hung-Sheng CHANG ,  Hsiang-Pang LI ,  Ting-Yu LIU ,  Chien-Hsin LIU ,  Nai-Ping KUO

    IPC: G06F3/06 ,  G06F12/08

    CPC classification number: G06F3/0619 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/00 ,  G06F11/14 ,  G06F12/0246 ,  G06F12/0806 ,  G06F2212/621

    Abstract: A memory device includes a memory controller and a non-volatile memory communicatively coupled to the memory controller and storing a mapping table and a journal table. The memory controller is configured to write data and a logical address of the data into the non-volatile memory, load mapping information related to the logical address of the data from the mapping table of the non-volatile memory into a mapping cache of the memory controller, update the mapping cache with an updated mapping relationship between the logical address of the data and a physical address of the data, and perform a journaling operation to write the updated mapping relationship into the journal table.

    Abstract translation: 存储器设备包括通信地耦合到存储器控制器并存储映射表和日志表的存储器控​​制器和非易失性存储器。 存储器控制器被配置为将数据和逻辑地址写入到非易失性存储器中，将与数据的逻辑地址相关的映射信息从非易失性存储器的映射表加载到存储器的映射高速缓存中 控制器，使用数据的逻辑地址与数据的物理地址之间的更新的映射关系来更新映射高速缓存，并且执行日志操作以将更新的映射关系写入日志表。

    MEMORY SUPPORTING MULTIPLE TYPES OF OPERATIONS
    3.
    发明公开
    MEMORY SUPPORTING MULTIPLE TYPES OF OPERATIONS 审中-公开

    公开(公告)号：US20230162763A1

    公开(公告)日：2023-05-25

    申请号：US17535021

    申请日：2021-11-24

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Shuo-Nan HUNG ,  Nai-Ping KUO ,  Chien-Hsin LIU

    IPC: G11C7/10

    CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1096 ,  G11C7/1069

    Abstract: A method of operating a memory comprising a plurality of memory planes is disclosed. Each memory plane includes at least one corresponding memory array. The method includes, for each memory plane of the plurality of memory planes, generating (i) a corresponding plane ready (PRDY) signal indicating a busy or a ready state of the corresponding memory plane, and (ii) a corresponding plane array ready (PARDY) signal indicating a busy or a ready state of the corresponding memory array of the corresponding memory plane, such that a plurality of PRDY signals and a plurality of PARDY signals are generated corresponding to the plurality of memory planes. Execution of a memory command for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PARDY signals.

    SOLID STATE DISK, DATA TRANSMITTING METHOD AND INTERMEDIARY CONTROLLER THEREOF
    5.
    发明公开
    SOLID STATE DISK, DATA TRANSMITTING METHOD AND INTERMEDIARY CONTROLLER THEREOF 审中-公开

    公开(公告)号：US20230176779A1

    公开(公告)日：2023-06-08

    申请号：US17541306

    申请日：2021-12-03

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Kuan-Chieh WANG ,  Shih-Chou JUAN ,  Nai-Ping KUO

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0656 ,  G06F3/0626 ,  G06F3/0679

    Abstract: A solid state disk, a data transmitting method and an intermediary controller thereof are provided. The solid state disk includes at least two flash memories, a SSD controller and an intermediary controller. The intermediary controller is connected between the flash memories and the SSD controller. The intermediary controller includes at least two flash interfaces, a customized interface and a data buffering unit. The flash interfaces are connected to the flash memories. The customized interface is connected to the SSD controller. The intermediary controller has a first clock domain and a second clock domain. The first clock domain is used for transmitting data from the flash memories to the data buffering unit. The second clock domain is used for transmitting data from the data buffering unit to the SSD controller. A frequency of the second clock domain is higher than a frequency of the first clock domain.

Patent Agency Ranking