公开(公告)号：US20220399361A1

公开(公告)日：2022-12-15

申请号：US17344661

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Tzung-Ting Han ,  Lo Yueh Lin ,  Chih-Chin Chang ,  Yu-Fong Huang ,  Yu-Hsiang Yeh

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

公开(公告)号：US12048154B2

公开(公告)日：2024-07-23

申请号：US17344661

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Tzung-Ting Han ,  Lo Yueh Lin ,  Chih-Chin Chang ,  Yu-Fong Huang ,  Yu-Hsiang Yeh

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

公开(公告)号：US09536887B2

公开(公告)日：2017-01-03

申请号：US14519906

申请日：2014-10-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Fong Huang ,  Kun-Mou Chan ,  Tzung-Ting Han

IPC: H01L21/70 ,  H01L29/788 ,  H01L23/48 ,  H01L27/115 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L27/11521 ,  H01L21/764 ,  H01L21/7682 ,  H01L27/11524 ,  H01L27/11568

Abstract: A process for fabricating a gate structure, the gate structure having a plurality of gates defined by a network of spaces. The word line (WL) spaces within a dense WL region having airgaps and those spaces outside of the dense WL being substantially free of airgaps. A gate structure having a silicide layer dispose across the plurality of gates is also provided.

Abstract translation: 一种用于制造栅极结构的工艺，所述栅极结构具有由空间网络限定的多个栅极。 具有气隙的密集WL区域内的字线（WL）空间，密集WL外部的那些空间基本上没有空气隙。 还提供了具有跨越多个栅极的硅化物层的栅极结构。