公开(公告)号：US20250107082A1

公开(公告)日：2025-03-27

申请号：US18474615

申请日：2023-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Chih-Kai Yang ,  Shih-Chin Lee ,  Tzung-Ting Han

IPC: H10B43/27

Abstract: A memory device includes a stack structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacked structure is located over a substrate. The stacked structure has an opening exposing a stepped structure of the stacked structure. The first stop layer covers the stepped structure and at least at least one portion of sidewalls of the opening. The dielectric layer fills the opening and covers the first stop layer. The separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the stepped structure. The memory device may be a 3D NAND flash memory with high capacity and high performance.

公开(公告)号：US20250105213A1

公开(公告)日：2025-03-27

申请号：US18474231

申请日：2023-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： Shao-En Chang ,  Tzung-Ting Han ,  Meng-Hsuan Weng ,  Chen-Yu Cheng

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/544 ,  H10B80/00

Abstract: Provided is a semiconductor device for manufacturing a 3D NAND flash memory with high capacity and high performance. The semiconductor device includes: a first device structure layer on a substrate; an interconnect structure layer on the first device structure layer, which includes first pads at a surface thereof; a second device structure layer on the interconnect structure layer, which includes second pads at a surface thereof; a pattern structure at an interface between the interconnect structure layer and the second device structure layer; a first seal ring at the surface of the interconnect structure layer, which surrounds the pattern structure; a second seal ring at the surface of the second device structure layer, which surrounds the pattern structure. The first pad is connected to the second pad, and the first seal ring is connected to the second seal ring.

公开(公告)号：US11690222B2

公开(公告)日：2023-06-27

申请号：US17102576

申请日：2020-11-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Kai Yang ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: A three-dimensional memory device and a method of manufacturing a three-dimensional memory device are provided. The method includes providing a precursor structure including a substrate, a multi-layered stack, a plurality of vertical channel pillars and a barrier structure. A first slit and a second slit are then formed in the multi-layered stack and the substrate along a first direction, in which the first slit and the second slit have a pitch between thereof, and the second slit cuts the barrier structure. A portion of the second insulating layers is then replaced with a plurality of conductive layers. A first slit structure and a second slit structure are then formed in the first slit and the second slit, in which the first slit structure and the second slit structure separate the vertical channel pillars in a second direction that is different from the first direction.

公开(公告)号：US11127756B2

公开(公告)日：2021-09-21

申请号：US16513344

申请日：2019-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Kai Yang ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L27/02 ,  H01L21/306 ,  H01L21/04

Abstract: Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.

公开(公告)号：US20210020650A1

公开(公告)日：2021-01-21

申请号：US16513344

申请日：2019-07-16

Applicant: MACRONIX International Co., Ltd.

Inventor： CHIH-KAI YANG ,  Tzung-Ting Han

IPC: H01L27/11582 ,  H01L21/04 ,  H01L21/306 ,  H01L27/02

Abstract: Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.

公开(公告)号：US20240284669A1

公开(公告)日：2024-08-22

申请号：US18169877

申请日：2023-02-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Chen-Yu Cheng ,  Tzung-Ting Han

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A memory device includes a substrate and a stack structure. A lower portion of the stack structure includes a first global selection line structure and a second global selection line structure. The first global selection line structure includes a first long strip, a first short strip and a first connection part connecting the first long strip and the first short strip. The first long strip and the second strip extend in a first direction, and the first connection part extends in a second direction different from the first direction. The first long strip passes through a staircase structure area from a first memory array area extending continuously to a second memory array area. The second global selection line structure is adjacent to the first global selection line structure and is divided into two portions separated from each other by the first connection part of the first global selection line structure.

公开(公告)号：US12069861B2

公开(公告)日：2024-08-20

申请号：US17836799

申请日：2022-06-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Kai Yang ,  Tzung-Ting Han

IPC: H10B41/10 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/562 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.

公开(公告)号：US20220399361A1

公开(公告)日：2022-12-15

申请号：US17344661

申请日：2021-06-10

Applicant: MACRONIX International Co., Ltd.

Inventor： Hong-Ji Lee ,  Tzung-Ting Han ,  Lo Yueh Lin ,  Chih-Chin Chang ,  Yu-Fong Huang ,  Yu-Hsiang Yeh

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

公开(公告)号：US10290543B1

公开(公告)日：2019-05-14

申请号：US15848986

申请日：2017-12-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Chang-Wen Jian ,  Hsiang-Lu Wu ,  Yu-Min Hung ,  Tzung-Ting Han

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/3213

Abstract: A method for manufacturing semiconductor device is provided. A substrate having a memory region and a capacitance region is provided. A plurality of word line structures are formed on the memory region of the substrate. A capacitance structure is formed on the capacitance region of the substrate. The word line structures and the capacitance structure each include a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer, a second dielectric layer on the first conductive layer, and a second conductive layer on the second dielectric layer. The second conductive layers of the word line structures close to an edge of the memory region and a portion of the second conductive layer of the capacitance structure are removed at the same time to form a trench exposing a portion of the second dielectric layer.

公开(公告)号：US20180366573A1

公开(公告)日：2018-12-20

申请号：US15624490

申请日：2017-06-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Fu-Hsing Chou ,  Yao-Fu Chan ,  Tzung-Ting Han

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device, a memory device, and a manufacturing method of the same are provided. The memory device includes a substrate, a floating gate, a gate insulation layer, an inter-gate dielectric layer, and a control gate. The control gate is a multi-layer structure with three or more layers, and at least one layer of the multi-layer structure is a metal silicide layer.