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公开(公告)号:US20170287921A1
公开(公告)日:2017-10-05
申请号:US15290470
申请日:2016-10-11
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor: CHI-PIN LU , PEI-CI JHANG , FU-HSING CHOU , CHIH-HSIUNG LEE
IPC: H01L27/115 , H01L21/762 , H01L21/02 , H01L29/06 , H01L21/027 , H01L21/306 , H01L21/768 , H01L29/36 , H01L29/04 , H01L21/311
CPC classification number: H01L27/11521 , H01L21/02164 , H01L21/02282 , H01L21/0273 , H01L21/30604 , H01L21/31111 , H01L21/76224 , H01L21/76802 , H01L27/11526 , H01L28/00 , H01L29/045 , H01L29/0649 , H01L29/36
Abstract: A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.
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公开(公告)号:US20210305273A1
公开(公告)日:2021-09-30
申请号:US16835360
申请日:2020-03-31
Applicant: MACRONIX International Co., Ltd.
Inventor: CHIH-HSIUNG LEE , Shaw-Hung Ku
IPC: H01L27/11582 , H01L27/11521 , H01L27/11556 , H01L21/28 , H01L27/11568 , H01L21/311 , H01L21/3213 , H01L21/02
Abstract: A memory device includes: a first bit line located on a dielectric layer and a second bit line located over the dielectric layer; a first word line and a second word line located between the first bit line and the second bit line; a source line located between the first word line and the second word line; a channel pillar penetrating through the first word line and the source line and the second word line, and being connected to the first bit line, the source line and the second bit line; and a charge storage structure including an upper portion surrounding an upper sidewall of the channel pillar and located between the second word line and the channel pillar; and a lower portion surrounding a lower sidewall of the channel pillar and located between the first word line and the channel pillar.
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