公开(公告)号：US11955416B2

公开(公告)日：2024-04-09

申请号：US17475439

申请日：2021-09-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Lu ,  Yun-Yuan Wang ,  Dai-Ying Lee

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49866 ,  H01L23/49877

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

公开(公告)号：US12255136B2

公开(公告)日：2025-03-18

申请号：US17748111

申请日：2022-05-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Lu ,  Yun-Yuan Wang ,  Ming-Hsiu Lee ,  Dai-Ying Lee

IPC: H01L23/522 ,  H01L23/532

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.

公开(公告)号：US20250087600A1

公开(公告)日：2025-03-13

申请号：US18808098

申请日：2024-08-19

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Hsien Lu ,  Ming-Hsiu Lee ,  Dai-Ying Lee

IPC: H01L23/00 ,  H01L21/3205 ,  H01L21/78 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor bonded structure including a first semiconductor chip, at least one second semiconductor chip, a stress adjusting structure, and a circuit layer is provided. The at least one second semiconductor chip is disposed on the first semiconductor chip and electrically connected to the first semiconductor chip. The stress adjusting structure is disposed in at least one of the first semiconductor chip and the at least one second semiconductor chip. The circuit layer is disposed on the at least one second semiconductor chip and the circuit layer is electrically connected to the at least one second semiconductor chip. A fabricating method of the semiconductor bonded structure is also provided. The semiconductor bonded structure may be applied to the fabrication of 3D NAND flash memory with high performance and high capacity.

公开(公告)号：US12283343B2

公开(公告)日：2025-04-22

申请号：US18064303

申请日：2022-12-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yun-Yuan Wang ,  Cheng-Hsien Lu ,  Po-Hao Tseng ,  Ming-Hsiu Lee

IPC: G11C7/10 ,  G11C7/14 ,  G11C8/08

Abstract: The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

公开(公告)号：US20240321686A1

公开(公告)日：2024-09-26

申请号：US18186212

申请日：2023-03-20

Applicant: MACRONIX International Co., Ltd.

Inventor： Cheng-Hsien Lu ,  Wei-Lun Weng ,  Ming-Hsiu Lee ,  Dai-Ying Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/5226 ,  H01L25/0657

Abstract: A semiconductor chip including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes semiconductor devices. The interconnect structure is disposed on the semiconductor substrate and electrically connected to the semiconductor devices. The semiconductor substrate or the interconnect structure includes at least one conductor, which includes a first conductive part and a second conductive part connected to the first conductive part. The first conductive part includes randomly oriented metal, and the second conductive part includes oriented metal. A bonding structure including the above-mentioned semiconductor chip and a fabricating method for fabricating the above-mentioned semiconductor chip are also provided.

公开(公告)号：US12094564B2

公开(公告)日：2024-09-17

申请号：US17817701

申请日：2022-08-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yun-Yuan Wang ,  Cheng-Hsien Lu ,  Dai-Ying Lee ,  Ming-Hsiu Lee ,  Feng-Min Lee

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/1006 ,  G11C7/109

Abstract: The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

公开(公告)号：US11816030B2

公开(公告)日：2023-11-14

申请号：US17722420

申请日：2022-04-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yun-Yuan Wang ,  Cheng-Hsien Lu ,  Ming-Hsiu Lee

IPC: G06F12/06 ,  G11C8/08 ,  G11C7/12 ,  H03K19/20

CPC classification number: G06F12/0646 ,  G11C7/12 ,  G11C8/08 ,  G06F2212/251 ,  H03K19/20

Abstract: A memory device, for executing an anneal computation with first state and a second state. The memory device includes a first memory array, a second memory array, a control circuit, a sensing circuit and a processing circuit. the control circuit selects a first horizontal row of memory units from the first memory array, and selects a second horizontal row of memory units from the second memory array. The sensing circuit computes a local energy value of the first state according to the current generated by the memory units of the first horizontal row, and computes a local energy value of the second state according to the current generated by the memory units of the second horizontal row. The processing circuit updates the first state and/or the second state according to the local energy value of the first state and the local energy value of the second state.