公开(公告)号：US12245428B2

公开(公告)日：2025-03-04

申请号：US17575418

申请日：2022-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Chia-Jung Chiu ,  Teng-Hao Yeh ,  Guan-Ru Lee

IPC: H10B41/27 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27 ,  H01L21/786

Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

公开(公告)号：US20230088149A1

公开(公告)日：2023-03-23

申请号：US17483527

申请日：2021-09-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Yuan Shen ,  Chia-Jung Chiu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/60

Abstract: Provided is a method of forming a three-dimensional (3D) memory device including: forming a discharging layer and a stack structure on a buffer layer; forming vertical channel structures in the stack structure; forming an opening in the stack structure, wherein the opening includes two first trenches extending along a X direction and two second trenches extending along a Y direction, and the two first trenches and the two second trenches are separated from each other; forming an insulating layer on a sidewall of the opening; removing the discharging layer exposed by the insulating layer to form a cavity connecting the two first trenches and the two second trenches, thereby forming a ring-shaped opening; performing a gate replacement process to replace sacrificial layers of the stack structure by conductive layers; and filling an isolating material in the ring-shaped opening to form an isolating ring structure.

公开(公告)号：US09123579B2

公开(公告)日：2015-09-01

申请号：US13914539

申请日：2013-06-10

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Chia-Jung Chiu ,  Chieh Lo

IPC: H01L27/115 ,  H01L27/105

CPC classification number: H01L27/11582 ,  H01L27/1052 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure.

Abstract translation: 半导体器件包括衬底，堆叠结构和晶体管。 衬底包括第一区域和第二区域。 堆叠结构形成在第一区域中的衬底上。 晶体管结构具有形成在第二区域中的栅极。 栅极结构的底部设置在距离衬底的高度处，该高度小于衬底和堆叠结构的底部之间的高度。

公开(公告)号：US20230225126A1

公开(公告)日：2023-07-13

申请号：US17575418

申请日：2022-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Chia-Jung Chiu ,  Teng-Hao Yeh ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

公开(公告)号：US11195847B2

公开(公告)日：2021-12-07

申请号：US16412596

申请日：2019-05-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Min-Feng Hung ,  Chia-Jung Chiu ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L21/762 ,  H01L29/417

Abstract: A memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.

公开(公告)号：US12255093B2

公开(公告)日：2025-03-18

申请号：US17743239

申请日：2022-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Yuan Shen ,  Chung-Hao Fu ,  Chia-Jung Chiu

IPC: H10B41/30 ,  H01L21/768 ,  H01L23/528 ,  H10B41/50 ,  H10B43/50

Abstract: The present disclosure provides a 3D memory structure such as 3D Flash memory structure applying for 3D AND flash memory and a method of forming the same. An etching stop layer is formed on a substrate including active elements. A stacked layer is formed on the etching stop layer. The stacked layer includes insulation layers and sacrificed layers stacked alternatively on the etching stop layer. A patterning process is performed on the stacked layer to form a first stacked structure above the active elements, a second stacked structure surrounding the first stacked structure, and a trench pattern separating the first stacked structure and the second stacked structure and exposing the etching stop layer. The trench pattern includes asymmetric inner sidewalls and outer sidewalls. The inner sidewalls define sidewalls of the first stacked structure. The outer sidewalls define sidewalls of the second stacked structure that face the first stacked structure.

公开(公告)号：US20240268112A1

公开(公告)日：2024-08-08

申请号：US18164623

申请日：2023-02-06

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Yuan Shen ,  Chia-Jung Chiu

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: Provided are a semiconductor structure for a 3D memory and a manufacturing method thereof. The semiconductor structure may be used in a 3D AND flash memory. The semiconductor structure includes a substrate having a memory array region and a staircase region, an insulating layer, a stacked structure and a vertical channel (VC) structure. The insulating layer is disposed on the substrate. The stacked structure is disposed on the insulating layer. The stacked structure includes first dielectric layers separated from each other, and the stacked structure in the staircase region has a staircase profile. The VC structure is disposed in the stacked structure in the memory array region and penetrates through the stacked structure. There is a vertical hole in the stacked structure and the insulating layer in the staircase region, and a third dielectric layer is filled in the vertical hole.

公开(公告)号：US20230369100A1

公开(公告)日：2023-11-16

申请号：US17743239

申请日：2022-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Yuan Shen ,  Chung-Hao Fu ,  Chia-Jung Chiu

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L21/76816 ,  H01L23/5283

Abstract: The present disclosure provides a 3D memory structure such as 3D Flash memory structure applying for 3D AND flash memory and a method of forming the same. An etching stop layer is formed on a substrate including active elements. A stacked layer is formed on the etching stop layer. The stacked layer includes insulation layers and sacrificed layers stacked alternatively on the etching stop layer. A patterning process is performed on the stacked layer to form a first stacked structure above the active elements, a second stacked structure surrounding the first stacked structure, and a trench pattern separating the first stacked structure and the second stacked structure and exposing the etching stop layer. The trench pattern includes asymmetric inner sidewalls and outer sidewalls. The inner sidewalls define sidewalls of the first stacked structure. The outer sidewalls define sidewalls of the second stacked structure that face the first stacked structure.

公开(公告)号：US20240373630A1

公开(公告)日：2024-11-07

申请号：US18312207

申请日：2023-05-04

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Yuan Shen ,  Guan-Ru Lee ,  Chia-Jung Chiu

IPC: H10B43/27

Abstract: A semiconductor device includes a staircase structure and an extension part. The stacked structure is located on a dielectric substrate. The staircase structure includes a plurality of conductive layers and a plurality of insulating layers stacked alternately on each other. The extension part is located at an end of the lower stair part of the staircase structure. The resistance value of the extension part is different from the resistance value of the plurality of conductive layers.

公开(公告)号：US20230371252A1

公开(公告)日：2023-11-16

申请号：US17742159

申请日：2022-05-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Kuan-Yuan Shen ,  Teng-Hao Yeh ,  Chia-Jung Chiu

IPC: H01L27/11526 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

CPC classification number: H01L27/11526 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578

Abstract: A three-dimension memory device, a memory circuit and a production method are provided. The three-dimension memory circuit includes a peripheral circuit, a metal layer, a buffer layer, a poly silicon layer, and a via array. The peripheral circuit is disposed on a substrate. The metal layer covers on the peripheral circuit and is electrically coupled to the peripheral circuit. The buffer layer is disposed on the metal layer. The poly silicon layer receives a reference ground voltage and is disposed on the buffer layer. The via array is disposed in the buffer layer and is used to electrically connect the metal layer and the poly silicon layer.