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公开(公告)号：US11903203B2
公开(公告)日：2024-02-13
申请号：US17461518
申请日：2021-08-30
发明人： Min-Feng Hung , Li-Yen Liang , Chia-Tze Huang
IPC分类号： H01L27/11582 , H10B43/27 , H10B43/10 , G11C16/04
CPC分类号： H10B43/27 , H10B43/10 , G11C16/0466
摘要： A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure. The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.
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公开(公告)号：US11638379B2
公开(公告)日：2023-04-25
申请号：US17511829
申请日：2021-10-27
发明人： Min-Feng Hung , Chia-Jung Chiu , Guan-Ru Lee
IPC分类号： H10B43/20 , H01L29/417 , H01L21/762
摘要： A method for forming a memory device is provided. The memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.
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公开(公告)号：US20220148919A1
公开(公告)日：2022-05-12
申请号：US17096539
申请日：2020-11-12
发明人： Min-Feng Hung
IPC分类号： H01L21/768 , H01L27/11582 , H01L23/528 , H01L23/00
摘要： A memory device is provided. The memory device includes a substrate, a stacked structure, and a contact. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on each other. Each of the plurality of conductive layers includes a main body and an end part. The main body is located in the memory array region and extends to the staircase region. The end part is connected to the main body and is located in the staircase region. A thickness of the end part is greater than a thickness of the main body. The contact lands on and is connected to the end part.
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4.发明申请公开(公告)号：US20180261622A1
公开(公告)日：2018-09-13
申请号：US15456700
申请日：2017-03-13
发明人： Yu-Wei Jiang , Min-Feng Hung , Jia-Rong Chiou
IPC分类号： H01L27/11582 , H01L27/11568
CPC分类号： H01L27/11582 , H01L27/11568
摘要： A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.
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公开(公告)号：US11521898B2
公开(公告)日：2022-12-06
申请号：US17096539
申请日：2020-11-12
发明人： Min-Feng Hung
IPC分类号： H01L21/768 , H01L27/11582 , H01L23/528 , H01L23/00 , H01L23/522 , H01L21/311 , H01L21/3213 , H01L27/11565
摘要： A memory device is provided. The memory device includes a substrate, a stacked structure, and a contact. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on each other. Each of the plurality of conductive layers includes a main body and an end part. The main body is located in the memory array region and extends to the staircase region. The end part is connected to the main body and is located in the staircase region. A thickness of the end part is greater than a thickness of the main body. The contact lands on and is connected to the end part.
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公开(公告)号：US11195847B2
公开(公告)日：2021-12-07
申请号：US16412596
申请日：2019-05-15
发明人： Min-Feng Hung , Chia-Jung Chiu , Guan-Ru Lee
IPC分类号： H01L27/11582 , H01L21/762 , H01L29/417
摘要： A memory device includes a substrate; a stack including a plurality of conductive layers and a plurality of insulating layers being alternatively stacked on the substrate; a plurality of memory structures formed on the substrate and penetrating the stack; a plurality of isolation structures formed on the substrate and penetrating the stack, wherein the isolation structures dividing the memory structures into a plurality of first memory structures and a plurality of second memory structures; and a plurality of common source pillars formed on the substrate and penetrating the stack, wherein the common source pillars directly contact the isolation structures.
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公开(公告)号：US10134754B2
公开(公告)日：2018-11-20
申请号：US15456700
申请日：2017-03-13
发明人： Yu-Wei Jiang , Min-Feng Hung , Jia-Rong Chiou
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11568
摘要： A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.
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公开(公告)号：US20240324199A1
公开(公告)日：2024-09-26
申请号：US18186961
申请日：2023-03-21
发明人： Min-Feng Hung
摘要： A memory device includes a stacked structure, a channel pillar, a plurality of conductive pillars, and a slit. The stacked structure is located on a dielectric substrate, and includes a plurality of conductive layers and a plurality of insulating layers stacked alternately. The channel pillar extends through the stacked structure. The plurality of conductive pillars are located in the channel pillar and electrically connected with the channel pillar. The charge storage structure is located between the plurality of conductive layers and the channel pillar. The slit is located in the stacked structure. The slit includes a body part and an extension part. The body part extends through the stacked structure. The extension part is connected to the body part and located between the stacked structure and the dielectric substrate. The memory may be applied in 3D AND flash memory.
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公开(公告)号：US20230077489A1
公开(公告)日：2023-03-16
申请号：US17477267
申请日：2021-09-16
发明人： Min-Feng Hung , Pi-Shan Tseng
IPC分类号： H01L27/11582 , H01L27/11556
摘要： A 3D AND flash memory device includes a gate stack structure, a plurality of channel pillars, a plurality of first conductive pillars and a plurality of second conductive pillars, a plurality of charge storage structures, and a plurality of isolation walls. The gate stack structure is located on a dielectric substrate and includes a plurality of gate layers and a plurality of insulating layers alternately stacked on each other. The channel pillars pass through the gate stack structure. The first conductive pillars and the second conductive pillars are located in the channel pillars and are electrically connected to the channel pillars. The charge storage structures are located between the gate layers and the channel pillar. The isolation walls are buried in the gate layers and cover the charge storage structures at outer sidewalls of the second conductive pillars.
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公开(公告)号：US20230066310A1
公开(公告)日：2023-03-02
申请号：US17461518
申请日：2021-08-30
发明人： Min-Feng Hung , Li-Yen Liang , Chia-Tze Huang
IPC分类号： H01L27/11582 , H01L27/11565
摘要： A 3D AND flash memory device includes a gate stack structure, a channel pillar, a first and a second conductive pillars, a charge storage structure, and a protective cap. The gate stack structure is disposed on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The channel pillar penetrates through the gate stack structure.
The first and the second conductive pillars are disposed in the channel pillar and penetrate through the gate stack structure, and the first and the second conductive pillars are separated from each other and each connected to the channel pillar. The charge storage structure is disposed between the gate layers and a sidewall of the channel pillar. The protective cap covers at least a top surface of the channel pillar and isolates the first conductive pillar and the second conductive pillar from a top gate layer of the gate layers.
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