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公开(公告)号：US20240039548A1
公开(公告)日：2024-02-01
申请号：US18206623
申请日：2023-06-07
Applicant: MEDIATEK INC.
Inventor： Wei-Hao Sun , Chuan-Hung Hsiao , Sung-Han Wen
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: A digital-to-analog converter (DAC) includes a plurality of DAC cells, a mismatch error sorting circuit, and a dynamic element matching (DEM) circuit. The mismatch error sorting circuit generates a sorting result of the plurality of DAC cells according to mismatch error levels of the plurality of DAC cells. The DEM circuit shapes the mismatch error levels of the plurality of DAC cells according to the sorting result of the plurality of DAC cells.
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公开(公告)号：US20180019758A1
公开(公告)日：2018-01-18
申请号：US15630942
申请日：2017-06-22
Applicant: MEDIATEK INC.
Inventor： Chuan-Hung Hsiao , Kuan-Ta Chen
CPC classification number: H03M1/742 , H03F3/2171 , H03F3/2173 , H03F3/3035 , H03F3/304 , H03F2203/45238 , H03M1/001
Abstract: A circuit applied to speaker includes a tri-level current DAC and a class D amplifier. The current DAC is arranged to receive a digital signal to generate a current signal, and the class D amplifier is arranged to directly receive the current from the current DAC and to amplify the current signal to generate an output signal. SNR performance is well improved class D amplifier due to small signal noise reduced by preceding tri-level DAC. In addition, the circuit further includes a driving stage, and a gate-drain voltage of a power transistor within the driving stage can be controlled to set the appropriate slew rate.
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3.发明公开公开(公告)号：US20230396152A1
公开(公告)日：2023-12-07
申请号：US18144839
申请日：2023-05-08
Applicant: MEDIATEK INC.
Inventor： Chuan-Hung Hsiao , Sung-Han Wen
Abstract: A noise filter circuit includes a filter and a transistor off-resistance control circuit. The filter includes a first transistor and a charge storage component. The first transistor has off-resistance when turned off or operated under sub-threshold region. A control terminal of the first transistor is not directly tied to a reference voltage, and is used to receive a first control voltage. The charge storage component has one terminal coupled to a connection terminal of the first transistor. The transistor off-resistance control circuit is coupled to the first transistor, and arranged to set the first control voltage for controlling the off-resistance of the first transistor.
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公开(公告)号：US10574212B2
公开(公告)日：2020-02-25
申请号：US16163625
申请日：2018-10-18
Applicant: MEDIATEK Inc.
Inventor： Sung-Han Wen , Chuan-Hung Hsiao
Abstract: A circuit for low-noise reference signal generation comprising a filter unit and a functional unit. The filter unit comprises a transistor and an energy storage component. The transistor comprises a first node, a second node, a control node and a body node. The first node is configured to receive an input signal. The second node is configured to output a filtered signal. The control node is configured to receive a control signal for controlling the transistor to turn on or off. The body node is configured to couple to the input signal, the output signal or a signal which is similar to the input signal or the output signal. The energy storage component is coupled to the second node of the transistor. The functional unit is coupled to the second node of the transistor and the energy storage component. The functional unit has high input impedance.
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公开(公告)号：US20190199300A1
公开(公告)日：2019-06-27
申请号：US16151339
申请日：2018-10-04
Applicant: MEDIATEK INC.
Inventor： Sung-Han Wen , Chien-Ming Chen , Chuan-Hung Hsiao
Abstract: The present invention provides a class-G amplifier, wherein the class-G amplifier includes an amplifier stage, an impedance detector and a power source. In the operations of the class-G amplifier, the amplifier stage is supplied by a supply voltage, and amplifies an input audio signal to generate an output audio signal, and the impedance detector is configured to detect an output impedance of the amplifier stage to generate a detection result, and the power source refers to the detection result to determine a level and a switching frequency of the supply voltage.
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230412181A1
公开(公告)日：2023-12-21
申请号：US18198283
申请日：2023-05-16
Applicant: MEDIATEK INC.
Inventor： Chuan-Hung Hsiao , SATYA NARAYANA GANTA , Sung-Han Wen , Kuan-Ta Chen
IPC: H03M1/06
CPC classification number: H03M1/0604
Abstract: A tri-level digital-to-analog converter (DAC) element includes a first DAC cell. The first DAC cell includes a first reference circuit, a second reference circuit, and a switch circuit. The first reference circuit provides a first reference signal. The second reference circuit provides a second reference signal. The first switch circuit receives a control input from an input port of the tri-level DAC element, and controls interconnection between the first reference circuit, the second reference circuit, and an output port of the tri-level DAC element according to the control input. During a period in which the tri-level DAC element operates in a “0” state, the first switch circuit is arranged to couple at least one of the first reference circuit and the second reference circuit to the output port of the tri-level DAC element.
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公开(公告)号：US10763884B2
公开(公告)日：2020-09-01
申请号：US16515056
申请日：2019-07-18
Applicant: MEDIATEK INC.
Inventor： Chuan-Hung Hsiao , Sung-Han Wen , Kuan-Ta Chen
Abstract: A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.
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公开(公告)号：US10686414B2
公开(公告)日：2020-06-16
申请号：US16151339
申请日：2018-10-04
Applicant: MEDIATEK INC.
Inventor： Sung-Han Wen , Chien-Ming Chen , Chuan-Hung Hsiao
Abstract: The present invention provides a class-G amplifier, wherein the class-G amplifier includes an amplifier stage, an impedance detector and a power source. In the operations of the class-G amplifier, the amplifier stage is supplied by a supply voltage, and amplifies an input audio signal to generate an output audio signal, and the impedance detector is configured to detect an output impedance of the amplifier stage to generate a detection result, and the power source refers to the detection result to determine a level and a switching frequency of the supply voltage.
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公开(公告)号：US20200028519A1
公开(公告)日：2020-01-23
申请号：US16515056
申请日：2019-07-18
Applicant: MEDIATEK INC.
Inventor： Chuan-Hung Hsiao , Sung-Han Wen , Kuan-Ta Chen
IPC: H03M1/68
Abstract: A digital-to-analog conversion circuit is used for converting a first digital input into a first analog output, and includes a segmentation circuit, a plurality of multi-bit dynamic element matching digital-to-analog converters (DEM DACs), and a combination circuit. The segmentation circuit applies segmentation to the first digital input to generate a plurality of code segments. The multi-bit DEM DACs convert the code segments into a plurality of DAC outputs, respectively, wherein the multi-bit DEM DACs include at least a first multi-bit DEM DAC and a second multi-bit DEM DAC, and the first multi-bit DEM DAC and the second multi-bit DEM DAC employ different DEM techniques. The combination circuit combines the DAC outputs to generate the first analog output.
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公开(公告)号：US10063251B2
公开(公告)日：2018-08-28
申请号：US15630942
申请日：2017-06-22
Applicant: MEDIATEK INC.
Inventor： Chuan-Hung Hsiao , Kuan-Ta Chen
CPC classification number: H03M1/742 , H03F3/2171 , H03F3/2173 , H03F3/3035 , H03F3/304 , H03F2203/45238 , H03M1/001
Abstract: A circuit applied to speaker includes a tri-level current DAC and a class D amplifier. The current DAC is arranged to receive a digital signal to generate a current signal, and the class D amplifier is arranged to directly receive the current from the current DAC and to amplify the current signal to generate an output signal. SNR performance is well improved class D amplifier due to small signal noise reduced by preceding tri-level DAC. In addition, the circuit further includes a driving stage, and a gate-drain voltage of a power transistor within the driving stage can be controlled to set the appropriate slew rate.
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