公开(公告)号：US20230260977A1

公开(公告)日：2023-08-17

申请号：US17962185

申请日：2022-10-07

Applicant: MediaTek Inc.

Inventor： Hsiao-Yun CHEN ,  Chi-Hung HUANG ,  Yao-Tsung HUANG ,  Cheng-Jyi CHANG ,  Sheng Chieh CHANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L25/162 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L25/165 ,  H01L24/73 ,  H01L24/80 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L28/75 ,  H01L28/90 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/19041 ,  H01L2924/19011 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/08235 ,  H01L2224/08265 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Various embodiments of a 3DIC die package, including trench capacitors integrated with IC dies, are disclosed. A 3DIC die package includes a first IC die and a second IC die disposed on the first IC die. The first IC die includes a substrate having a first surface and a second surface opposite to the first surface, a first active device disposed on the first surface of the substrate, and a passive device disposed on the second surface of the substrate. The passive device includes a plurality of trenches disposed in the substrate and through the second surface of the substrate, first and second conductive layers disposed in the plurality of trenches and on the second surface of the substrate, and a first dielectric layer disposed between the first and second conductive layers. The second IC die includes a second active device.

公开(公告)号：US20240096861A1

公开(公告)日：2024-03-21

申请号：US18454220

申请日：2023-08-23

Applicant: MEDIATEK INC.

Inventor： Che-Hung KUO ,  Hsiao-Yun CHEN ,  Wen-Pin CHU ,  Chun-Hsiang HUANG

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5385 ,  H01L28/90 ,  H10B80/00 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes first semiconductor die, a second semiconductor die and a memory package. The first semiconductor die and the second semiconductor die are stacked on each other. The first semiconductor die includes a first interface and a third interface. The first interface overlaps and is electrically connected to the second interface arranged on the second semiconductor die. The third interface is arranged on a first edge of the first semiconductor die. The memory package is disposed beside the first semiconductor die, wherein the memory package is electrically connected to the first semiconductor die by the third interface.

公开(公告)号：US20230125239A1

公开(公告)日：2023-04-27

申请号：US17934233

申请日：2022-09-22

Applicant: MEDIATEK INC.

Inventor： Hsiao-Yun CHEN ,  Yao-Tsung HUANG ,  Cheng-Jyi CHANG

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second through via, a molding material, a second semiconductor die, and a second redistribution layer. The first semiconductor die is disposed over the first redistribution layer and includes a first through via having a first width. The second through via is adjacent to the first semiconductor die and has a second width. The second width is greater than the first width. The molding material surrounds the first semiconductor die and the second through via. The second semiconductor die is disposed over the molding material and is electrically coupled to the first through via and the second through via. The second redistribution layer is disposed over the second semiconductor die.

公开(公告)号：US20230046413A1

公开(公告)日：2023-02-16

申请号：US17812786

申请日：2022-07-15

Applicant: MEDIATEK INC.

Inventor： Tai-Yu CHEN ,  Chin-Lai CHEN ,  Hsiao-Yun CHEN ,  Wen-Sung HSU ,  Haw-Kuen SU ,  Duen-Yi HO ,  Bo-Jiun YANG ,  Ta-Jen YU ,  Bo-Hao MA

IPC: H01L25/10 ,  H01L25/18

Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.