公开(公告)号：US20130256878A1

公开(公告)日：2013-10-03

申请号：US13835701

申请日：2013-03-15

Applicant: MEDIATEK INC.

Inventor： Wen-Sung HSU ,  Tzu-Hung LIN ,  Ta-Jen YU

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor package includes a substrate having a die attach surface. A die is mounted on die attach surface of the substrate via a conductive pillar bump. The die comprises a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, wherein the length of the first edge is different from that of the second edge from a plan view.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括半导体封装，其包括具有管芯附接表面的衬底。 模具通过导电柱凸块安装在基板的芯片附着表面上。 芯片包括电耦合到导电柱凸起的金属焊盘，其中金属焊盘具有基本上垂直于第一边缘的第一边缘和第二边缘，其中第一边缘的长度与第二边缘的长度不同于 平面图。

公开(公告)号：US20230282626A1

公开(公告)日：2023-09-07

申请号：US18163417

申请日：2023-02-02

Applicant: MEDIATEK INC.

Inventor： Tai-Yu CHEN ,  Bo-Jiun YANG ,  Tsung-Yu PAN ,  Yin-Fa CHEN ,  Ta-Jen YU ,  Bo-Hao MA ,  Wen-Sung HSU ,  Yao-Pang HSU

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L23/14

CPC classification number: H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/147 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1511 ,  H01L2924/152

Abstract: A high-bandwidth package-on-package (HBPoP) structure includes a first package structure and a second package structure disposed over the first package structure. The first package structure includes a first package substrate, a semiconductor die, an interposer, and a molding material. The first package substrate is formed of a silicon and/or ceramic material. The semiconductor die is disposed over the first package substrate. The interposer is disposed over the semiconductor die and is formed of a silicon and/or ceramic material. The molding material is disposed between the first package substrate and the interposer and surrounds the semiconductor die.

公开(公告)号：US20150264814A1

公开(公告)日：2015-09-17

申请号：US14205836

申请日：2014-03-12

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ta-Jen YU

IPC: H05K1/18 ,  H05K3/18 ,  H05K3/30 ,  H05K3/10 ,  H01L23/00 ,  H05K3/00

CPC classification number: H01L21/485 ,  H01F17/00 ,  H01F17/0006 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/705 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/642 ,  H01L23/645 ,  H01L23/66 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/12042 ,  H01L2924/1206 ,  H01L2924/1421 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/2064 ,  H05K1/165 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/107 ,  H05K3/188 ,  H05K3/303 ,  H05K2201/10098 ,  H01L2924/00

Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.

Abstract translation: 本发明提供半导体封装和用于制造用于半导体封装的基座的方法。 该半导体封装包括一个基座。 底座有一个装置附着面。 射频（RF）设备嵌入在基座中。 RF设备靠近设备连接表面。

公开(公告)号：US20150145127A1

公开(公告)日：2015-05-28

申请号：US14611354

申请日：2015-02-02

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Tzu-Hung LIN ,  Ta-Jen YU

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. A conductive trace is disposed on the substrate. A conductive pillar bump is disposed on the conductive trace, wherein the conductive bump is coupled to a die. In another configuration, a first conductive trace is disposed on the substrate, and a second conductive trace is disposed on the substrate. In the second configuration, a conductive pillar bump disposed on the second conductive trace, connecting to a conductive bump or a metal pad of the semiconductor die. A first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate, and a die is disposed over the first conductive trace.

Abstract translation: 提供半导体封装。 在一种配置中，半导体封装包括衬底。 导电迹线设置在基板上。 导电柱凸块设置在导电迹线上，其中导电凸块连接到管芯。 在另一种结构中，第一导电迹线设置在衬底上，并且第二导电迹线设置在衬底上。 在第二构造中，设置在第二导电迹线上的导电柱凸块连接到半导体管芯的导电凸块或金属焊盘。 第一导电结构设置在第二导电迹线和导电柱突起之间或第二导电迹线和衬底之间，并且管芯设置在第一导电迹线上。

公开(公告)号：US20240274517A1

公开(公告)日：2024-08-15

申请号：US18418419

申请日：2024-01-22

Applicant: MEDIATEK INC.

Inventor： Fa-Chuan CHEN ,  Ta-Jen YU ,  Bo-Jiun YANG ,  Tsung-Yu PAN ,  Tai-Yu CHEN ,  Nai-Wei LIU ,  Shih-Chin LIN ,  Wen-Sung HSU

IPC: H01L23/498 ,  H01L21/28 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/28132 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0652 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2924/01029 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/351

Abstract: A semiconductor package structure includes a first component, a bonding structure on the first component, a second component connected to the first component, and a copper connector on the second component. The bonding structure includes a copper base on the first component and copper protruding portions on the copper base. The second component is connected to the first component by bonding the copper protruding portions to the copper connector, and the copper protruding portions are in contact with the copper connector.

公开(公告)号：US20230046413A1

公开(公告)日：2023-02-16

申请号：US17812786

申请日：2022-07-15

Applicant: MEDIATEK INC.

Inventor： Tai-Yu CHEN ,  Chin-Lai CHEN ,  Hsiao-Yun CHEN ,  Wen-Sung HSU ,  Haw-Kuen SU ,  Duen-Yi HO ,  Bo-Jiun YANG ,  Ta-Jen YU ,  Bo-Hao MA

IPC: H01L25/10 ,  H01L25/18

Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.

公开(公告)号：US20200312732A1

公开(公告)日：2020-10-01

申请号：US16903458

申请日：2020-06-17

Applicant: MEDIATEK INC.

Inventor： Yen-Yao CHI ,  Nai-Wei LIU ,  Ta-Jen YU ,  Tzu-Hung LIN ,  Wen-Sung HSU ,  Shih-Chin LIN

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

公开(公告)号：US20180076121A1

公开(公告)日：2018-03-15

申请号：US15817780

申请日：2017-11-20

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ta-Jen YU

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5384 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/205 ,  H01L2924/00012 ,  H01L2924/0001

Abstract: A package substrate is provided. The package substrate includes a dielectric layer and a passive component embedded in the dielectric layer and contacting the dielectric layer. A circuit layer is embedded in the dielectric layer and has a first surface aligned with a second surface of the dielectric layer. A conductive structure is embedded in the dielectric layer and electrically connected to the passive component and the circuit layer. A chip package is also provided.

公开(公告)号：US20160343632A1

公开(公告)日：2016-11-24

申请号：US15225927

申请日：2016-08-02

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Ming-Chieh LIN ,  Ta-Jen YU

IPC: H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16238 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/8146 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01109 ,  H01L2924/012

Abstract: A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.

Abstract translation: 芯片封装包括具有彼此电分离的多个导电部分的图案化导电板，设置在图案化导电板的上表面上的多个导电焊盘，其中从一个导电焊盘的表面向着 相应的一个导电焊盘的内部部分，设置在导电焊盘上的芯片，设置在图案化导电板的下表面上的多个导电凸块，其中每个导电凸块电连接到 图案化导电板的导电部分和部分地围绕导电凸块的绝缘支撑层。

公开(公告)号：US20240332266A1

公开(公告)日：2024-10-03

申请号：US18405195

申请日：2024-01-05

Applicant: MEDIATEK INC.

Inventor： Che-Hung KUO ,  Ta-Jen YU ,  Chi-Hung HUANG

IPC: H01L25/10 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor device is provided. The semiconductor device includes a bottom package and a top package. The top package is mounted on the bottom package. At least one portion of the top package protrudes from a sidewall of the bottom package. The semiconductor device further includes a passive device mounted on a protruding region of the portion of the top package.