公开(公告)号：US11222691B2

公开(公告)日：2022-01-11

申请号：US16813723

申请日：2020-03-09

Applicant: MediaTek Inc.

Inventor： Tun-Fei Chien ,  Chia-Wei Wang

IPC: G11C11/4093 ,  G11C11/418 ,  G11C11/419

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

公开(公告)号：US20210280237A1

公开(公告)日：2021-09-09

申请号：US16813723

申请日：2020-03-09

Applicant: MediaTek Inc.

Inventor： Tun-Fei Chien ,  Chia-Wei Wang

IPC: G11C11/418 ,  G11C11/419

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

公开(公告)号：US10181358B2

公开(公告)日：2019-01-15

申请号：US15492014

申请日：2017-04-20

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/00 ,  G11C17/18 ,  G11C7/06

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.

公开(公告)号：US09728276B2

公开(公告)日：2017-08-08

申请号：US14750102

申请日：2015-06-25

Applicant: MediaTek Inc.

Inventor： Shi-Wei Chang ,  Chia-Wei Wang

IPC: G11C7/00 ,  G11C29/44

CPC classification number: G11C29/4401

Abstract: An embodiment of the invention provides an integrated circuit including a core circuit and a memory. The core circuit executes operations of the integrated circuit. The memory stores a subsystem and a repair system. When the repair system runs, the repair system detects whether there is a defect in the memory. When the repair system detects the defect, the repair system repairs the defect, and when the repair system does not detect the defect, a fake defect is injected in the memory to verify whether the repair system runs correctly.

公开(公告)号：US20220165330A1

公开(公告)日：2022-05-26

申请号：US17543547

申请日：2021-12-06

Applicant: MediaTek Inc.

Inventor： Tun-Fei Chien ,  Chia-Wei Wang

IPC: G11C11/418 ,  G11C11/419

Abstract: Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

公开(公告)号：US10332574B2

公开(公告)日：2019-06-25

申请号：US15818768

申请日：2017-11-21

Applicant: MEDIATEK INC.

Inventor： Chia-Wei Wang

IPC: G11C8/10 ,  G11C7/22 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G06F17/50 ,  G11C7/12 ,  G06F13/16

Abstract: An embedded memory includes a memory interface circuit, a cell array, and a peripheral circuit. The memory interface circuit receives at least a clock signal, a non-clock signal, and a setup-hold time control setting, and includes a programmable path delay circuit that is used to set a path delay of at least one of a clock path and a non-clock path according to the setup-hold time control setting. The clock path is used to deliver the clock signal, and the non-clock path is used to deliver the non-clock signal. The peripheral circuit is used to access the cell array according to at least the clock signal provided from the clock path and the non-clock signal.

公开(公告)号：US20160320821A1

公开(公告)日：2016-11-03

申请号：US15138462

申请日：2016-04-26

Applicant: MediaTek Inc.

Inventor： Hugh Thomas Mair ,  Yi-Te Chiu ,  Che-Wei Wu ,  Lee-Kee Yong ,  Chia-Wei Wang ,  Cheng-Hsing Chien ,  Uming Ko

IPC: G06F1/28

CPC classification number: G06F1/3296 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/172

Abstract: A processing device performs dual-rail power equalization for its memory cell array and logic circuitry. The memory cell array is coupled to a first power rail through a first switch to receive a first voltage level. The logic circuitry is coupled to a second power rail through a second switch to receive a second voltage level that is different from the first voltage level. The processing device also includes a power switch coupled to at least the second power rail and operative to be enabled to equalize voltage supplied to the memory cell array and the logic circuitry.

Abstract translation: 处理装置为其存储单元阵列和逻辑电路执行双轨功率均衡。 存储单元阵列通过第一开关耦合到第一电源轨，以接收第一电压电平。 逻辑电路通过第二开关耦合到第二电源轨，以接收不同于第一电压电平的第二电压电平。 处理装置还包括耦合到至少第二电力轨的功率开关，并且被操作以使得能够均衡提供给存储单元阵列和逻辑电路的电压。

公开(公告)号：US09449679B2

公开(公告)日：2016-09-20

申请号：US14680289

申请日：2015-04-07

Applicant: MediaTek Inc.

Inventor： Shu-Hsuan Lin ,  Chia-Wei Wang

IPC: G11C7/00 ,  G11C11/418 ,  G11C7/12 ,  G11C11/417 ,  G11C29/02 ,  G11C11/41

CPC classification number: G11C11/418 ,  G11C7/12 ,  G11C11/41 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028

Abstract: A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.

Abstract translation: 存储器件包括第一信号线; 存储单元阵列，分成第一区域和第二区域，并且分别在第一区域和第二区域中具有多个第一存储单元和第二存储单元。 多个第一和第二存储器单元耦合第一信号线，并且每个具有参考节点。 第一电压调节电路调节多个第一存储单元的参考节点处的电压，其中第一电压调整电路包括：耦合在多个第一存储单元的参考节点与地之间的第一开关，由地址 信号; 以及耦合到所述多个第一存储器单元中的参考节点的第一偏置元件。 第二电压调整电路调节多个第二存储单元的参考节点处的电压。

公开(公告)号：US09025394B2

公开(公告)日：2015-05-05

申请号：US13869171

申请日：2013-04-24

Applicant: MediaTek Inc.

Inventor： Shu-Hsuan Lin ,  Chia-Wei Wang

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/417 ,  G11C29/02 ,  G11C11/41

CPC classification number: G11C11/418 ,  G11C7/12 ,  G11C11/41 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028

Abstract: A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second area. The first and second memory cells are coupled the first signal line. Each of the first and second memory cells has a reference node. The first voltage adjustment circuit adjusts voltages at the reference nodes of the first memory cells. The second voltage adjustment circuit adjusts voltages at the reference nodes of the second memory cells. The reference nodes of the first memory cells are coupled to a ground through the first voltage adjustment circuit. The reference nodes of the second memory cells are coupled to the ground through the second voltage adjustment circuit.

Abstract translation: 提供存储器件。 存储器件包括第一信号线，存储单元阵列，第一和第二电压调节电路。 存储单元阵列被划分为第一和第二区域，并且包括第一区域中的第一存储单元和第二区域中的第二存储单元。 第一和第二存储器单元耦合第一信号线。 第一和第二存储器单元中的每一个具有参考节点。 第一电压调节电路调节第一存储器单元的参考节点处的电压。 第二电压调节电路调节第二存储单元的参考节点处的电压。 第一存储单元的参考节点通过第一电压调节电路耦合到地。 第二存储单元的参考节点通过第二电压调节电路耦合到地。

公开(公告)号：US10770161B2

公开(公告)日：2020-09-08

申请号：US16211524

申请日：2018-12-06

Applicant: MEDIATEK Inc.

Inventor： Chia-Wei Wang ,  Shu-Lin Lai ,  Yi-Te Chiu

IPC: G11C17/00 ,  G11C17/18 ,  G11C7/06

Abstract: A sense amplifier for reading a via Read-Only Memory (Via-ROM) is provided. The sense amplifier includes a read circuit, an adaptive keeper circuit and a leakage monitor circuit. The read circuit is connected to the via-ROM. The adaptive keeper circuit is connected to the read circuit. The leakage monitor circuit is connected to the adaptive keeper circuit for forming a current mirror, such that the adaptive keeper circuit compensates a read voltage of a memory cell whose via is opened when a bit-line leakage is happened.