METHODS AND SYSTEMS FOR HANDLING INTERRUPT REQUESTS
    1.
    发明申请
    METHODS AND SYSTEMS FOR HANDLING INTERRUPT REQUESTS 审中-公开
    处理中断请求的方法和系统

    公开(公告)号:US20170039148A1

    公开(公告)日:2017-02-09

    申请号:US15186325

    申请日:2016-06-17

    Applicant: Mediatek Inc.

    CPC classification number: G06F13/24 Y02D10/14

    Abstract: Systems, methods, and computer readable medium are provided that improve the management of interrupt requests in multiple processor computer systems. Interrupt requests can be classified into three categories and the structure of the categories provide for specifying a list that needs to be migrated. The list can contain only those interrupt requests that can be handled by some of the processors that will never unplug or based on affinity. When a processor is about to unplug, the computer system can migrate that list. The system can also manage the other interrupt requests.

    Abstract translation: 提供了系统,方法和计算机可读介质,其改进了在多处理器计算机系统中的中断请求的管理。 中断请求可以分为三类,类别的结构提供了指定需要迁移的列表。 该列表只能包含那些可以由一些处理器处理的中断请求,这些中断请求将永远不会拔掉或基于亲和力。 当处理器即将拔出时,计算机系统可以迁移该列表。 系统还可以管理其他中断请求。

    SEMICONDUCTOR PACKAGE STRUCTURE
    3.
    发明申请

    公开(公告)号:US20220223491A1

    公开(公告)日:2022-07-14

    申请号:US17545015

    申请日:2021-12-08

    Applicant: MEDIATEK INC.

    Abstract: A semiconductor package structure includes a first redistribution layer, a semiconductor die, a thermal spreader, and a molding material. The semiconductor die is disposed over the first redistribution layer. The thermal spreader is disposed over the semiconductor die. The molding material surrounds the semiconductor die and the thermal spreader.

    Environment-Aware Cache Flushing Mechanism
    4.
    发明申请
    Environment-Aware Cache Flushing Mechanism 有权
    环境意识缓存刷新机制

    公开(公告)号:US20170010965A1

    公开(公告)日:2017-01-12

    申请号:US14935477

    申请日:2015-11-09

    Applicant: MediaTek Inc.

    Abstract: A computing system performs an environment-aware cache flushing method. When a processor in the system receives a signal to flush at least a portion of the caches to the system memory, the processor determines a flushing mechanism among multiple candidate flushing mechanisms. The processor also determines one or more of the active processors in the system for performing the flushing mechanism. The determinations are based on the extent of flushing indicated in the signal and a runtime environment that includes the number of active processors. The system then flushes the caches to the system memory according to the flushing mechanism.

    Abstract translation: 计算系统执行环境感知缓存刷新方法。 当系统中的处理器接收到将至少一部分高速缓存冲洗到系统存储器的信号时,处理器确定多个候选冲洗机构之间的冲洗机构。 处理器还确定系统中的一个或多个活动处理器以执行冲洗机构。 这些确定是基于信号中指示的冲洗程度和包括活动处理器数量的运行时环境。 系统然后根据冲洗机制将缓存刷新到系统内存。

    Energy Efficient Multi-Cluster System and Its Operations
    5.
    发明申请
    Energy Efficient Multi-Cluster System and Its Operations 有权
    节能多集群系统及其运行

    公开(公告)号:US20160139964A1

    公开(公告)日:2016-05-19

    申请号:US14936686

    申请日:2015-11-10

    Applicant: MediaTek Inc.

    Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

    Abstract translation: 具有不同能量效率特性的处理器核心的多集群系统被配置为以高效率运行,从而可以满足性能和功率要求。 该系统包括组中层次结构中的多个处理器核心。 组的层次结构包括:多个一级组,每个一级组,包括具有相同能量效率特性的一个或多个处理器核心,以及被配置为由一级调度器分配任务的每个一级组; 一个或多个2级组,每个2级组包括相应的1级组,具有不同能量效率特性的相同2级组的不同级别1组中的处理器核心,以及被配置为 由相应的二级调度程序分配任务; 以及包括一个或多个2级组并被配置为由3级调度器分配任务的3级组。

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