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    Adaptive flow prioritization
    1.
    发明授权
    Adaptive flow prioritization 有权

    公开(公告)号：US10601714B2

    公开(公告)日：2020-03-24

    申请号：US15963118

    申请日：2018-04-26

    Applicant: Mellanox Technologies TLV Ltd.

    Inventor： Eyal Srebro ,  Sagi Kuks ,  Liron Mula ,  Barak Gafni ,  Benny Koren ,  George Elias ,  Itamar Rabenstein ,  Niv Aibester

    IPC: H04L12/801 ,  H04L12/863 ,  H04L12/865 ,  H04L12/927 ,  H04L12/851

    Abstract: A method for communication includes receiving and forwarding packets in multiple flows to respective egress interfaces of a switching element for transmission to a network. For each of one or more of the egress interfaces, in each of a succession of arbitration cycles, a respective number of the packets in each of the plurality of the flows that are queued for transmission through the egress interface is assessed, and the flows for which the respective number is less than a selected threshold to a first group, while assigning the flows for which the respective number is equal to or greater than the selected threshold are assigned to a second group. The received packets that have been forwarded to the egress interface and belong to the flows in the first group are transmitted with a higher priority than the flows in the second group.

    Switch arbitration based on distinct-flow counts
    2.
    发明授权
    Switch arbitration based on distinct-flow counts 有权

    公开(公告)号：US10218642B2

    公开(公告)日：2019-02-26

    申请号：US15469643

    申请日：2017-03-27

    Applicant: Mellanox Technologies TLV Ltd.

    Inventor： Liron Mula ,  Sagi Kuks ,  George Elias ,  Eyal Srebro ,  Ofir Merdler ,  Amiad Marelli ,  Lion Levi ,  Oded Zemer ,  Yoav Benros

    IPC: H04L12/935 ,  H04L12/933 ,  H04L12/937 ,  H04L12/931 ,  H04L12/861

    Abstract: A network switch includes circuitry and multiple ports, including multiple input ports and at least one output port, configured to connect to a communication network. The circuitry includes multiple distinct-flow counters, which are each associated with a respective input port and with the output port, and which are configured to estimate respective distinct-flow counts of distinct data flows received via the respective input ports and destined to the output port. The circuitry is configured to store packets that are destined to the output port and were received via the multiple input ports in multiple queues, to determine a transmission schedule for the packets stored in the queues, based on the estimated distinct-flow counts, and to transmit the packets via the output port in accordance with the determined transmission schedule.

    Reusing switch ports for external buffer network
    4.
    发明授权
    Reusing switch ports for external buffer network 有权

    公开(公告)号：US10951549B2

    公开(公告)日：2021-03-16

    申请号：US16294958

    申请日：2019-03-07

    Applicant: MELLANOX TECHNOLOGIES TLV LTD.

    Inventor： George Elias ,  Gil Levy ,  Liron Mula ,  Aviv Kfir ,  Benny Koren ,  Sagi Kuks

    IPC: H04L12/861 ,  H04L12/935

    Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

    Throughput in a crossbar network element by modifying mappings between time slots and ports
    5.
    发明授权
    Throughput in a crossbar network element by modifying mappings between time slots and ports 有权

    公开(公告)号：US10938715B2

    公开(公告)日：2021-03-02

    申请号：US16436945

    申请日：2019-06-11

    Applicant: MELLANOX TECHNOLOGIES TLV LTD.

    Inventor： Ofir Merdler ,  George Elias ,  Yuval Shpigelman ,  Eyal Srebro ,  Sagi Kuks

    IPC: H04L12/773 ,  H04L12/935 ,  H04L12/933 ,  H04L12/861

    Abstract: A network element includes output ports, a crossbar fabric and a scheduler. The output ports are organized in groups of multiple output ports selectable over predefined time slots in accordance with a cyclic mapping assigned to each group. In each time slot, the crossbar fabric routes to fabric outputs data received from the buffers via fabric inputs, in accordance with a routing plan. The scheduler determines and applies the routing plan for transmitting packets from the buffers to the communication network via the crossbar fabric and output ports. When in a given time slot, a required readout rate from a given buffer exceeds a maximum rate, the scheduler selects a group of the output ports to which the given buffer is routed in that time slot, and modifies the cyclic mapping for that group to reduce the required readout rate from the given buffer in the given time slot.

    Time division communication via optical switch fabric
    7.
    发明申请
    Time division communication via optical switch fabric 有权

    公开(公告)号：US20210384998A1

    公开(公告)日：2021-12-09

    申请号：US17413555

    申请日：2019-01-03

    Applicant: Mellanox Technologies TLV Ltd.

    Inventor： Liron Mula ,  Elad Mentovich ,  Paraskevas Bakopoulos ,  Eitan Zahavi ,  Sagi Kuks

    IPC: H04J3/06 ,  H04Q11/00

    Abstract: A network element (36) includes circuitry and at least one port (72). The at least one port is coupled to an optical fabric (32) including one or more optical switches (40) that provide optical paths between the at least one port and multiple destination nodes, at predefined time slots. The circuitry is configured to hold a schedule plan (84) that specifies which of the destination nodes are accessible via the optical fabric at which of the time slots, to queue packets that are destined to the destination nodes, and to transmit the queued packets via the at least one port in accordance with the schedule plan.

    Reusing Switch Ports for External Buffer Network
    8.
    发明申请
    Reusing Switch Ports for External Buffer Network 审中-公开

    公开(公告)号：US20200287846A1

    公开(公告)日：2020-09-10

    申请号：US16294958

    申请日：2019-03-07

    Applicant: MELLANOX TECHNOLOGIES TLV LTD.

    Inventor： George Elias ,  Gil Levy ,  Liron Mula ,  Aviv Kfir ,  Benny Koren ,  Sagi Kuks

    IPC: H04L12/861 ,  H04L12/935

    Abstract: An Integrated Circuit (IC) includes multiple ports and packet processing circuitry. The ports are configured to serve as ingress ports and egress ports for receiving and transmitting packets from and to a communication network. The packet processing circuitry is configured to forward the packets between the ingress ports and the egress ports, to read an indication that specifies whether the IC is to operate in an internal buffer configuration or in an off-chip buffer configuration, when the indication specifies the internal buffer configuration, to buffer the packets internally to the IC, and, when the indication specifies the off-chip buffer configuration, to configure one or more of the ports for connecting to a memory system external to the IC, and for buffering at least some of the packets in the memory system, externally to the IC.

    Time division communication via optical switch fabric
    10.
    发明授权
    Time division communication via optical switch fabric 有权

    公开(公告)号：US12149340B2

    公开(公告)日：2024-11-19

    申请号：US17413555

    申请日：2019-01-03

    Applicant: Mellanox Technologies TLV Ltd.

    Inventor： Liron Mula ,  Elad Mentovich ,  Paraskevas Bakopoulos ,  Eitan Zahavi ,  Sagi Kuks

    IPC: H04J3/06 ,  H04Q11/00

    Abstract: A network element (36) includes circuitry and at least one port (72). The at least one port is coupled to an optical fabric (32) including one or more optical switches (40) that provide optical paths between the at least one port and multiple destination nodes, at predefined time slots. The circuitry is configured to hold a schedule plan (84) that specifies which of the destination nodes are accessible via the optical fabric at which of the time slots, to queue packets that are destined to the destination nodes, and to transmit the queued packets via the at least one port in accordance with the schedule plan.

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