公开(公告)号：US20210067448A1

公开(公告)日：2021-03-04

申请号：US16559658

申请日：2019-09-04

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tom Remen ,  Nir Monovich ,  Gil Levy ,  Aviv Kfir ,  Linor Nehab

IPC: H04L12/743 ,  H04L12/741 ,  H04L29/06

Abstract: A network element includes ports, a hardware fabric, a packet classifier and control logic. The ports are configured to transmit and receive packets over a network. The fabric is configured to forward the packets between the ports. The packet classifier is configured to receive at least some of the packets and to specify an action to be applied to a packet in accordance with a set of rules. The classifier includes (i) multiple Ternary Content Addressable Memories (TCAMs), each TCAM configured to match the packet to a respective subset of the set of rules and to output a match result, and (ii) circuitry configured to specify the action to be applied to the packet based on match results produced for the packet by the multiple TCAMs, and based on a priority defined among the multiple TCAMs. The control logic is configured to apply the specified action to the packet.

公开(公告)号：US10944675B1

公开(公告)日：2021-03-09

申请号：US16559658

申请日：2019-09-04

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tom Remen ,  Nir Monovich ,  Gil Levy ,  Aviv Kfir ,  Linor Nehab

IPC: H04L12/743 ,  H04L29/06 ,  H04L12/741

Abstract: A network element includes ports, a hardware fabric, a packet classifier and control logic. The ports are configured to transmit and receive packets over a network. The fabric is configured to forward the packets between the ports. The packet classifier is configured to receive at least some of the packets and to specify an action to be applied to a packet in accordance with a set of rules. The classifier includes (i) multiple Ternary Content Addressable Memories (TCAMs), each TCAM configured to match the packet to a respective subset of the set of rules and to output a match result, and (ii) circuitry configured to specify the action to be applied to the packet based on match results produced for the packet by the multiple TCAMs, and based on a priority defined among the multiple TCAMs. The control logic is configured to apply the specified action to the packet.

公开(公告)号：US20210042251A1

公开(公告)日：2021-02-11

申请号：US16537576

申请日：2019-08-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Lion Levi ,  Aviv Kfir ,  Idan Matari ,  Ran Shani ,  Zachy Haramaty ,  Nir Monovich ,  Matty Kadosh

IPC: G06F13/28 ,  G06F13/40 ,  H04L12/861 ,  H04L12/725

Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.

公开(公告)号：US10938720B2

公开(公告)日：2021-03-02

申请号：US16420217

申请日：2019-05-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Gil Levy ,  Nir Monovich

IPC: H04L12/747 ,  H04L12/741

Abstract: A network element includes multiple ports, a memory, multiple processors and cache-flushing circuitry. The multiple ports are configured to serve as ingress and egress ports for receiving and transmitting packets from and to a network. The memory is configured to store a forwarding table including rules that specify forwarding of the packets from the ingress ports to the egress ports. The multiple processors are configured to process the packets in accordance with the rules. The two or more cache memories are each configured to cache a respective copy of one or more of the rules, for use by the multiple processors. The cache-flushing circuitry is configured to trigger flushing operations of copies of rules in the cache memories in response to changes in the forwarding table, and to reduce a likelihood of simultaneous accesses to the forwarding table for updating multiple cache memories, by de-correlating or diluting the flushing operations.

公开(公告)号：US10915479B1

公开(公告)日：2021-02-09

申请号：US16537576

申请日：2019-08-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Lion Levi ,  Aviv Kfir ,  Idan Matari ,  Ran Shani ,  Zachy Haramaty ,  Nir Monovich ,  Matty Kadosh

IPC: G06F13/28 ,  H04L12/725 ,  H04L12/861 ,  G06F13/40

Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.

公开(公告)号：US20200374230A1

公开(公告)日：2020-11-26

申请号：US16420217

申请日：2019-05-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Gil Levy ,  Nir Monovich

IPC: H04L12/747 ,  H04L12/741

Abstract: A network element includes multiple ports, a memory, multiple processors and cache-flushing circuitry. The multiple ports are configured to serve as ingress and egress ports for receiving and transmitting packets from and to a network. The memory is configured to store a forwarding table including rules that specify forwarding of the packets from the ingress ports to the egress ports. The multiple processors are configured to process the packets in accordance with the rules. The two or more cache memories are each configured to cache a respective copy of one or more of the rules, for use by the multiple processors. The cache-flushing circuitry is configured to trigger flushing operations of copies of rules in the cache memories in response to changes in the forwarding table, and to reduce a likelihood of simultaneous accesses to the forwarding table for updating multiple cache memories, by de-correlating or diluting the flushing operations.