公开(公告)号：US20220263776A1

公开(公告)日：2022-08-18

申请号：US17175716

申请日：2021-02-15

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Idan Matari ,  Niv Aibester ,  George Elias ,  Lion Levi

IPC: H04L12/861 ,  H04L12/823

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

公开(公告)号：US11252027B2

公开(公告)日：2022-02-15

申请号：US16750019

申请日：2020-01-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Ortal Ben-Moshe ,  Lion Levi ,  Itamar Rabenstein ,  Idan Matari ,  Noam Michaelis ,  Ofir Merdler ,  Evyatar Romlet

IPC: H04L12/24 ,  H04L12/911 ,  H04L1/00 ,  H04L29/08

Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.

公开(公告)号：US10915479B1

公开(公告)日：2021-02-09

申请号：US16537576

申请日：2019-08-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Lion Levi ,  Aviv Kfir ,  Idan Matari ,  Ran Shani ,  Zachy Haramaty ,  Nir Monovich ,  Matty Kadosh

IPC: G06F13/28 ,  H04L12/725 ,  H04L12/861 ,  G06F13/40

Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.

公开(公告)号：US20210042251A1

公开(公告)日：2021-02-11

申请号：US16537576

申请日：2019-08-11

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Lion Levi ,  Aviv Kfir ,  Idan Matari ,  Ran Shani ,  Zachy Haramaty ,  Nir Monovich ,  Matty Kadosh

IPC: G06F13/28 ,  G06F13/40 ,  H04L12/861 ,  H04L12/725

Abstract: A network element includes one or more ports for communicating over a network, a processor and packet processing hardware. The packet processing hardware is configured to transfer packets to and from the ports, and further includes data-transfer circuitry for data transfer with the processor. The processor and the data-transfer circuitry are configured to transfer between one another (i) one or more communication packets for transferal between the ports and the processor and (ii) one or more databases for transferal between the packet processing hardware and the processor, by (i) translating, by the processor, the transferal of both the communication packets and the databases into work elements, and posting the work elements on one or more work queues in a memory of the processor, and (ii) using the data-transfer circuitry, executing the work elements so as to transfer both the communication packets and the databases.

公开(公告)号：US11558316B2

公开(公告)日：2023-01-17

申请号：US17175716

申请日：2021-02-15

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Idan Matari ,  Niv Aibester ,  George Elias ,  Lion Levi

IPC: H04L12/861 ,  H04L49/90 ,  H04L47/32 ,  H04L49/9047

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

公开(公告)号：US20210234753A1

公开(公告)日：2021-07-29

申请号：US16750019

申请日：2020-01-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Ortal Ben-Moshe ,  Lion Levi ,  Itamar Rabenstein ,  Idan Matari ,  Noam Michaelis ,  Ofir Merdler ,  Evyatar Romlet

IPC: H04L12/24 ,  H04L12/911 ,  H04L1/00 ,  H04L29/08

Abstract: A network element includes a plurality of ports, multiple computational modules, configurable forwarding circuitry and a central block. The ports include child ports coupled to child network elements or network nodes and parent ports coupled to parent network elements. The computational modules collectively perform a data reduction operation of a data reduction protocol. The forwarding circuitry interconnects among ports and computational modules. The central block receives a request indicative of child ports, a parent port, and computational modules required for performing reduction operations on data received via the child ports, for producing reduced data destined to the parent port, to derive from the request a topology that interconnects among the child ports, parent port and computational modules for performing the data reduction operations and to forward the reduced data for transmission to the selected parent port, and to configure the forwarding circuitry to apply the topology.