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    MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL
    7.
    发明公开
    MEMORY DEVICES WITH A LOWER EFFECTIVE PROGRAM VERIFY LEVEL 审中-公开

    公开(公告)号：US20240071484A1

    公开(公告)日：2024-02-29

    申请号：US18234429

    申请日：2023-08-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Massimo Ernesto Bertuccio ,  Sead Zildzic, JR.

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10

    CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10

    Abstract: A memory device includes an array of memory cells, a plurality of access lines, and a controller. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line is connected to a control gate of a respective memory cell of each string of series-connected memory cells. The controller is configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a first target level. The controller is further configured to apply a first voltage level to a first access line connected to the selected memory cell, and apply a second voltage level higher than the first voltage level to a second access line adjacent to the first access line. The controller is further configured to apply a third voltage level between the first voltage level and the second voltage level to a third access line adjacent to the first access line and connected to an erased memory cell, and sense a first threshold voltage of the selected memory cell.

    Memories for mitigating program disturb
    8.
    发明授权
    Memories for mitigating program disturb 有权

    公开(公告)号：US11200958B2

    公开(公告)日：2021-12-14

    申请号：US17091379

    申请日：2020-11-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Daniele Cantarelli ,  Augusto Benvenuti ,  Massimo Ernesto Bertuccio

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32 ,  G11C7/12

    Abstract: Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.

    MEMORIES FOR MITIGATING PROGRAM DISTURB
    9.
    发明申请
    MEMORIES FOR MITIGATING PROGRAM DISTURB 有权

    公开(公告)号：US20210065827A1

    公开(公告)日：2021-03-04

    申请号：US17091379

    申请日：2020-11-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Daniele Cantarelli ,  Augusto Benvenuti ,  Massimo Ernesto Bertuccio

    IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32

    Abstract: Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.

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