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    MANAGING THE PROGRAMMING OF AN OPEN TRANSLATION UNIT
    2.
    发明申请
    MANAGING THE PROGRAMMING OF AN OPEN TRANSLATION UNIT 有权

    公开(公告)号：US20250118364A1

    公开(公告)日：2025-04-10

    申请号：US18988243

    申请日：2024-12-19

    Applicant: Micron Technology, Inc.

    Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

    IPC: G11C11/56

    Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE
    3.
    发明公开
    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230145358A1

    公开(公告)日：2023-05-11

    申请号：US17978890

    申请日：2022-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Jeffrey S. McNeil ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Sead Zildzic ,  Violante Moschiano ,  James Fitzpatrick

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0679 ,  G06F3/064

    Abstract: A method includes receiving, by control logic of a memory device, a copyback clear command from a processing device; causing, in response to the copyback clear command, a page buffer to perform a dual-strobe read operation on first memory cells configured as single-level cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage that are sensed between threshold voltage distributions of the first memory cells; causing the page buffer to determine a number of one bit values within the threshold voltage distributions detected in a threshold voltage range between the first/second threshold voltages; and causing, in response to the number of one bit values not satisfying a threshold criterion, a copyback of data in the first memory cells to second memory cells configured as high-level cells without intervention from the processing device.

    SCAN OPTIMIZATION USING DATA SELECTION ACROSS WORDLINE OF A MEMORY ARRAY
    4.
    发明申请
    SCAN OPTIMIZATION USING DATA SELECTION ACROSS WORDLINE OF A MEMORY ARRAY 有权

    公开(公告)号：US20230012644A1

    公开(公告)日：2023-01-19

    申请号：US17946207

    申请日：2022-09-16

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Sead Zildzic ,  Junwyn A. Lacsao ,  Paing Z. Htet

    IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4074 ,  G11C11/408 ,  G11C29/50

    Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.

    READ WINDOW SIZE
    7.
    发明申请
    READ WINDOW SIZE 审中-公开

    公开(公告)号：US20200210259A1

    公开(公告)日：2020-07-02

    申请号：US16234256

    申请日：2018-12-27

    Applicant: Micron Technology, Inc.

    Inventor： Jung Sheng Hoei ,  Peter Sean Feeley ,  Sampath K. Ratnam ,  Sead Zildzic ,  Kishore Kumar Muchherla

    IPC: G06F11/07 ,  G11C16/26 ,  G11C16/34

    Abstract: A processing device in a memory system receives a memory command indicating a read window size and a first read voltage and identifies a read window for a first data block of the memory component having the read window size and centered at the first read voltage. The processing device determines whether a number of bit flips for the first data block within the read window exceeds an error threshold and, in response to the number of bit flips exceeding the error threshold, refreshes data stored on the first data block of the memory component.

    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE
    9.
    发明申请
    COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY DEVICE 有权

    公开(公告)号：US20250004645A1

    公开(公告)日：2025-01-02

    申请号：US18886901

    申请日：2024-09-16

    Applicant: Micron Technology, Inc.

    Inventor： Jeffrey S. McNeil ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Sead Zildzic ,  Violante Moschiano ,  James Fitzpatrick

    IPC: G06F3/06 ,  G11C16/34 ,  G11C29/52

    Abstract: A memory device includes array(s) of memory cells including first memory cells configured as single-level cell memory and second memory cells configured as higher-level cell memory. Page buffer(s) are coupled with the array(s). Logic is coupled with the page buffer(s) and to cause, in response to receipt of a copyback clear command, a page buffer to perform a dual-strobe read operation on the first memory cells, the dual-strobe read operation including a soft strobe at a first threshold voltage and a hard strobe at a second threshold voltage. The logic causes the page buffer to determine a number of one bit values within a threshold voltage range between the first threshold voltage and the second threshold voltage. The logic causes, responsive to the number of one bit values not satisfying a threshold criterion, a copyback be performed of data in the first memory cells to the second memory cells.

    Two-tier defect scan management
    10.
    发明授权
    Two-tier defect scan management 有权

    公开(公告)号：US12105967B2

    公开(公告)日：2024-10-01

    申请号：US17894794

    申请日：2022-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

    IPC: G06F3/06

    CPC classification number: G06F3/0629 ,  G06F3/0625 ,  G06F3/0679

    Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

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