公开(公告)号：US20230363148A1

公开(公告)日：2023-11-09

申请号：US17740064

申请日：2022-05-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yuki Munetaka ,  Tsuyoshi Tomoyama

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894

Abstract: An apparatus includes a plurality of memory cells in a memory cell array region; a plurality of word lines extending across the memory cell array region and a peripheral region in which no memory cell is arranged; a plurality of contact plugs on even numbered ones of the plurality of word lines in the peripheral region, respectively; and a plurality of insulating walls on odd numbered ones of the plurality of word lines in the peripheral region, respectively.

公开(公告)号：US20190386010A1

公开(公告)日：2019-12-19

申请号：US16010779

申请日：2018-06-18

Applicant: Micron Technology, Inc.

Inventor： Tsuyoshi Tomoyama

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US09741723B2

公开(公告)日：2017-08-22

申请号：US14852852

申请日：2015-09-14

Applicant: Micron Technology, Inc.

Inventor： Tsuyoshi Tomoyama

IPC: H01L21/70 ,  H01L21/76 ,  H01L27/108

CPC classification number: H01L27/10897 ,  H01L21/762 ,  H01L27/10814

Abstract: A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a memory cell area and a peripheral circuit area. The semiconductor device 1 has a semiconductor substrate 2 on which a memory cell area MC defined by a peripheral isolation region 3c. The memory cell area MC has multiple cell active regions k defined by multiple cell isolation regions 3a, 3b. Guard active regions GLa, GLb made of the semiconductor substrate are disposed in the border between the memory cell area MC and the peripheral isolation region 3c to separate the memory cell isolation regions 3a, 3b from the peripheral isolation region 3c.

公开(公告)号：US11037800B2

公开(公告)日：2021-06-15

申请号：US16351274

申请日：2019-03-12

Applicant: Micron Technology, inc.

Inventor： Tsuyoshi Tomoyama ,  Hiromitsu Oshima ,  Tomohiro Iwaki

IPC: H01L21/321 ,  H01L21/3213 ,  H01L27/108 ,  H01L21/56 ,  H01L21/033

Abstract: Some embodiments include a method of patterning a target material. An assembly is provided which has a masking material over the target material. First lines are formed over the assembly. The first lines extend along a first direction and are laterally spaced from one another by first spaces. Second lines are formed over the first lines. The second lines extend along a second direction which crosses the first direction, and are laterally spaced from one another by second spaces. The second lines cross the first lines at first crossing regions. The second spaces cross the first spaces at second crossing regions. A pattern includes the first and second crossing regions. The pattern is transferred into the masking material to form holes in the masking material in locations directly under the first and second crossing regions. The holes are extended into the target material.

公开(公告)号：US20200294814A1

公开(公告)日：2020-09-17

申请号：US16351274

申请日：2019-03-12

Applicant: Micron Technology, Inc.

Inventor： Tsuyoshi Tomoyama ,  Hiromitsu Oshima ,  Tomohiro Iwaki

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/56 ,  H01L27/108

Abstract: Some embodiments include a method of patterning a target material. An assembly is provided which has a masking material over the target material. First lines are formed over the assembly. The first lines extend along a first direction and are laterally spaced from one another by first spaces. Second lines are formed over the first lines. The second lines extend along a second direction which crosses the first direction, and are laterally spaced from one another by second spaces. The second lines cross the first lines at first crossing regions. The second spaces cross the first spaces at second crossing regions. A pattern includes the first and second crossing regions. The pattern is transferred into the masking material to form holes in the masking material in locations directly under the first and second crossing regions. The holes are extended into the target material.

公开(公告)号：US12114490B2

公开(公告)日：2024-10-08

申请号：US17558323

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Naoyoshi Kobayashi ,  Tsuyoshi Tomoyama

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/488

Abstract: An apparatus includes a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; and a plurality of word-lines extending in parallel across the memory cell region and the peripheral region; a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region.

公开(公告)号：US20240274526A1

公开(公告)日：2024-08-15

申请号：US18440404

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Tsuyoshi Tomoyama ,  Protyush Sahu ,  Hiromitsu Oshima ,  Jeffery B. Hull ,  Satoru Sugiyama ,  Soichi Sugiura

IPC: H01L23/522 ,  H01L23/528 ,  H10B12/00

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482 ,  H10B12/485

Abstract: A method used in forming memory circuitry comprises forming transistors of individual memory cells. The transistors individually comprise one source/drain region and another source/drain region. The one and another source/drain regions comprise conductively-doped monocrystalline semiconductive material. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Masking material is formed directly above the one and another source/drain regions. The masking material has openings there-through that extend to and are individually directly above individual of the one source/drain regions. Conductively-doped monocrystalline semiconductor material is epitaxially grown from the conductively-doped monocrystalline semiconductive material of the individual one source/drain regions within individual of the openings to form conductive islands that are individually directly above and directly against the individual one source/drain regions in the individual openings. Storage elements of the individual memory cells are formed. The storage elements individually are above and electrically coupled to the individual one source/drain regions through individual of the conductive islands comprising the epitaxially-grown conductively-doped monocrystalline semiconductor material. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230200058A1

公开(公告)日：2023-06-22

申请号：US17558323

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Naoyoshi Kobayashi ,  Tsuyoshi Tomoyama

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10891 ,  H01L27/10894

Abstract: An apparatus includes a substrate; a memory cell region provided over the substrate; a peripheral region provided over the substrate and adjacent to the memory cell region; and a plurality of word-lines extending in parallel across the memory cell region and the peripheral region; a first insulating film covering top surfaces of the plurality of word-lines in each of the memory cell region and the peripheral region and covering side surfaces of upper portions of the plurality of word-lines in the peripheral region without covering side surfaces of the upper portions of the plurality of word-lines in the memory cell region.

公开(公告)号：US11798837B2

公开(公告)日：2023-10-24

申请号：US17491825

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Tsuyoshi Tomoyama ,  Keisuke Otsuka

IPC: H01L21/768 ,  H10B12/00

CPC classification number: H01L21/76811 ,  H10B12/485 ,  H10B12/03

Abstract: Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.

公开(公告)号：US11056494B2

公开(公告)日：2021-07-06

申请号：US16653658

申请日：2019-10-15

Applicant: Micron Technology, Inc.

Inventor： Tsuyoshi Tomoyama

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having a paired-memory-cell-region within a memory-array-region. The paired-memory-cell-region includes a bitline-contact-structure between a first charge-storage-device-contact-structure and a second charge-storage-device-contact-structure. A first insulative region is between the bitline-contact-structure and the first charge-storage-device-contact-structure. A second insulative region is between the bitline-contact-structure and the second charge-storage-device-contact-structure. The first and second insulative regions both include a first semiconductor material which is in a nonconductive configuration. A transistor gate is over a peripheral region proximate the memory-array-region. The transistor gate has a second semiconductor material which is a same semiconductor composition and thickness as the first semiconductor material, but which is in a conductive configuration. Some embodiments include methods of forming integrated assemblies.