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    APPARATUS INCLUDING CLOCK INPUT BUFFER
    1.
    发明申请
    APPARATUS INCLUDING CLOCK INPUT BUFFER 有权

    公开(公告)号：US20250118356A1

    公开(公告)日：2025-04-10

    申请号：US18751840

    申请日：2024-06-24

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yasuhiro Takai ,  Shuichi Tsukada

    IPC: G11C11/4093 ,  G11C11/4076

    Abstract: Embodiments of the disclosure provide an apparatus comprising: first and second input transistors of a first type and first and second load transistors of a second type coupled in series, respectively; at least one resistor coupled to gate nodes of the load transistors; and first and second capacitive devices. Gate nodes of the first and second input transistors are coupled to first and second inputs, respectively. The first input transistor and the first load transistor are coupled to a first output. The second input transistor and the second load transistor are coupled to a second output. The gate nodes of the first and second load transistors are coupled to a bias voltage through the resistor. The first and second capacitive devices are coupled to the first and second inputs and to the gate nodes of the first and second load transistors, respectively.

    PHASE LOCK CIRCUITRY USING FREQUENCY DETECTION
    2.
    发明申请
    PHASE LOCK CIRCUITRY USING FREQUENCY DETECTION 审中-公开

    公开(公告)号：US20200313678A1

    公开(公告)日：2020-10-01

    申请号：US16368706

    申请日：2019-03-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yasuhiro Takai ,  Maksim Kuzmenka ,  Mani Balakrishnan ,  Martin Brox

    IPC: H03L7/087 ,  H03K5/135 ,  H03K5/14 ,  G11C7/22 ,  H03L7/099

    Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

    PHASE LOCK CIRCUITRY USING FREQUENCY DETECTION
    3.
    发明申请
    PHASE LOCK CIRCUITRY USING FREQUENCY DETECTION 有权

    公开(公告)号：US20210075428A1

    公开(公告)日：2021-03-11

    申请号：US17099114

    申请日：2020-11-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yasuhiro Takai ,  Maksim Kuzmenka ,  Mani Balakrishnan ,  Martin Brox

    IPC: H03L7/087 ,  H03K5/135 ,  H03L7/099 ,  G11C7/22 ,  H03K5/14

    Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal, To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

    INPUT RECEIVER CIRCUIT
    5.
    发明申请
    INPUT RECEIVER CIRCUIT 审中-公开

    公开(公告)号：US20170148495A1

    公开(公告)日：2017-05-25

    申请号：US14947122

    申请日：2015-11-20

    Applicant: Micron Technology, Inc.

    Inventor： Yasuhiro Takai

    IPC: G11C7/10

    CPC classification number: G11C7/1084 ,  G11C7/109 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2254

    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes an input node; a reference node supplied with a reference voltage; first, second, third and fourth nodes; a first transistor coupled between the first node and the second node, the first transistor having a gate coupled to the input node; a second transistor coupled between the first node and the third node, the second transistor having a gate coupled to the reference node; a third transistor coupled between the second node and the fourth node, the third transistor having a gate coupled to the third node; a fourth transistor coupled between the third node and the fourth node, the fourth transistor having a gate coupled to the third node; and a capacitor coupled between the input node and the third node.

    Phase lock circuitry using frequency detection
    6.
    发明授权
    Phase lock circuitry using frequency detection 有权

    公开(公告)号：US11251796B2

    公开(公告)日：2022-02-15

    申请号：US17099114

    申请日：2020-11-16

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yasuhiro Takai ,  Maksim Kuzmenka ,  Mani Balakrishnan ,  Martin Brox

    IPC: H03L7/087 ,  H03K5/135 ,  H03L7/099 ,  H03K5/14 ,  G11C7/22

    Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

    Input buffer
    8.
    发明授权
    Input buffer 有权
    输入缓冲区

    公开(公告)号：US09431094B1

    公开(公告)日：2016-08-30

    申请号：US14987355

    申请日：2016-01-04

    Applicant: Micron Technology, Inc.

    Inventor： Yasuhiro Takai

    IPC: G11C16/04 ,  G11C11/4093 ,  G11C11/4076

    CPC classification number: G11C11/4093 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/4076 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008

    Abstract: Apparatuses including a data input circuit of a semiconductor device are described. An example apparatus includes a first transistor that receives a reference voltage, a second transistor that receives an input signal, cross-couple type transistors, diode-connect type transistors and resistors. The cross-couple type resistors include a third transistor having a gate coupled to a drain of the second transistor, and a fourth transistor having a gate coupled to a drain of the first transistor. The diode-connect type transistors include a fifth transistor having a drain coupled to a drain of the third transistor, and a sixth transistor having a drain coupled to a drain of the fourth transistor. The resistors include a first resistor coupled between a gate and the drain of the fifth transistor and a second resistor coupled between a gate and the drain of the sixth transistor.

    Abstract translation: 描述包括半导体器件的数据输入电路的装置。 示例性装置包括接收参考电压的第一晶体管，接收输入信号的第二晶体管，交叉耦合型晶体管，二极管连接型晶体管和电阻器。 交叉耦合型电阻器包括具有耦合到第二晶体管的漏极的栅极的第三晶体管和具有耦合到第一晶体管的漏极的栅极的第四晶体管。 二极管连接型晶体管包括具有耦合到第三晶体管的漏极的漏极的第五晶体管，以及耦合到第四晶体管的漏极的漏极的第六晶体管。 电阻器包括耦合在第五晶体管的栅极和漏极之间的第一电阻器和耦合在第六晶体管的栅极和漏极之间的第二电阻器。

    Systems and methods for a centralized command address input buffer
    9.
    发明授权
    Systems and methods for a centralized command address input buffer 有权

    公开(公告)号：US10403335B1

    公开(公告)日：2019-09-03

    申请号：US15997356

    申请日：2018-06-04

    Applicant: Micron Technology, Inc.

    Inventor： Yutaka Uemura ,  Yasuhiro Takai

    IPC: G11C7/10 ,  G11C7/22

    Abstract: An apparatus may include a first pad and a first input circuit coupled to the first pad. The first input circuitry may include a first signal propagation path that couples to the first pad, a latch circuit, a second signal propagation path that couples to the latch circuit, and a gate circuitry coupling between the first and second signal propagation paths. The first signal propagation path may have first signal propagation time and the second signal propagation path may have second signal propagation time that is greater than the first propagation time.

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