公开(公告)号：US11531552B2

公开(公告)日：2022-12-20

申请号：US15425632

申请日：2017-02-06

申请人： Microsoft Technology Licensing, LLC

发明人： Gagan Gupta ,  Douglas C. Burger

IPC分类号： G06F9/38 ,  G06F9/30

摘要： Systems and methods are disclosed for allocating resources to contexts in block-based processor architectures. In one example of the disclosed technology, a processor is configured to spatially allocate resources between multiple contexts being executed by the processor, including caches, functional units, and register files. In a second example of the disclosed technology, a processor is configured to temporally allocate resources between multiple contexts, for example, on a clock cycle basis, including caches, register files, and branch predictors. Each context is guaranteed access to its allocated resources to avoid starvation from contexts competing for resources of the processor. A results buffer can be used for folding larger instruction blocks into portions that can be mapped to smaller-sized instruction windows. The results buffer stores operand results that can be passed to subsequent portions of an instruction block.

公开(公告)号：US10963379B2

公开(公告)日：2021-03-30

申请号：US15887640

申请日：2018-02-02

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas C. Burger ,  Aaron L. Smith ,  Gagan Gupta ,  David T. Harper

IPC分类号： G06F12/08 ,  G06F12/0804 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0844

摘要： Systems and methods are disclosed for performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.

公开(公告)号：US20200089503A1

公开(公告)日：2020-03-19

申请号：US16224600

申请日：2018-12-18

申请人： Microsoft Technology Licensing, LLC

发明人： Gagan Gupta ,  David T. Harper

IPC分类号： G06F9/38 ,  G06F9/30

摘要： Systems and methods are disclosed for executing instructions with a block-based processor. Instructions can be executed in any order as their dependencies arrive, but the individual instructions are committed in a serial fashion. Further, exception handling can be performed by storing transient state for an instruction block and resuming by restoring the transient state. This allows programmers to see intermediate state for the instruction block before the subject block has committed. In one examples of the disclosed technology, a method of operating a processor executing a block-based instruction set architecture includes executing at least one instruction encoded for an instruction block, responsive to determining that an individual instruction of the instruction block can commit, advancing a commit frontier for the instruction block to include all instructions in the instruction block that can commit, and committing one or more instructions inside the advanced commit frontier.

公开(公告)号：US12064741B2

公开(公告)日：2024-08-20

申请号：US17815380

申请日：2022-07-27

申请人： MICROSOFT TECHNOLOGY LICENSING, LLC

发明人： Bichlien Nguyen ,  Karin Strauss ,  Gagan Gupta ,  Richard Rouse

IPC分类号： B01J19/00

CPC分类号： B01J19/0046 ,  B01J19/0006 ,  B01J2219/0018 ,  B01J2219/00454 ,  B01J2219/00596 ,  B01J2219/00612 ,  B01J2219/00626 ,  B01J2219/00637 ,  B01J2219/00653 ,  B01J2219/00713 ,  B01J2219/00722 ,  B01J2219/00725

摘要： Polymers synthesized by solid-phase synthesis are selectively released from a solid support by reversing the bias of spatially addressable electrodes. Change in the current and voltage direction at one or more of the spatially addressable electrodes changes the ionic environment which triggers cleavage of linkers that leads to release of the attached polymers. The spatially addressable electrodes may be implemented as CMOS inverters embedded in an integrated circuit (IC). The IC may contain an array of many thousands of spatially addressable electrodes. Control circuity may independently reverse the bias on any of the individual electrodes in the array. This provides fine-grained control of which polymers are released from the solid support. Examples of polymers that may be synthesized on this type of array include oligonucleotides and peptides.

公开(公告)号：US11734480B2

公开(公告)日：2023-08-22

申请号：US16224718

申请日：2018-12-18

申请人： Microsoft Technology Licensing, LLC

发明人： Gagan Gupta ,  Rathijit Sen ,  Hossein Golestani

IPC分类号： G06F30/30 ,  G06F11/34

CPC分类号： G06F30/30 ,  G06F11/3447 ,  G06F11/3466

摘要： Embodiments described herein are directed to a microarchitecture modeling tool configured to model and analyze a microarchitecture using a dependency graph. The dependency graph may be generated based on an execution trace of a program and a microarchitecture definition that specifies various features and/or characteristics of the microarchitecture on which the execution trace is based. The dependency graph includes vertices representing different microarchitectural events. The vertices are coupled via edges representing a particular dependency therebetween. The edges are associated with a cost for performing microarchitectural event(s) corresponding to the vertices coupled thereto. The dependency graph also takes into account various policies for structural hazards of the microarchitecture. The microarchitecture modeling tool analyzes the costs associated with each of the edges to determine a design metric of the microarchitecture. A user is enabled to modify various features of the dependency graph to analyze different design choices and/or optimizations to the microarchitecture.

公开(公告)号：US11366769B1

公开(公告)日：2022-06-21

申请号：US17185855

申请日：2021-02-25

申请人： Microsoft Technology Licensing, LLC

发明人： Artur Klauser ,  Jason S. Wohlgemuth ,  Abolade Gbadegesin ,  Gagan Gupta ,  Soheil Ebadian ,  Thomas Philip Speier ,  Derek Chiou

IPC分类号： G06F13/12 ,  G06F9/30

摘要： Enabling peripheral device messaging via application portals in processor-based devices is disclosed herein. In one embodiment, a processor-based device comprises a processing element (PE) including an application portal configured to logically operate as a message store, and that is exposed as an application portal address within an address space visible to a peripheral device that is communicatively coupled to the processor-based device. Upon receiving a message directed to the application portal address from the peripheral device, an application portal control circuit enqueues the message in the application portal. In some embodiments, the PE may further provide a dequeue instruction that may be executed as part of the application, and that results in a top element of the application portal being dequeued and transmitted to the application. Some embodiments may provide further mechanisms for sending success and/or failure notifications, and/or for informing the application that the message has been enqueued.

公开(公告)号：US10956162B2

公开(公告)日：2021-03-23

申请号：US16456836

申请日：2019-06-28

申请人： Microsoft Technology Licensing, LLC

发明人： Robert Douglas Clancy ,  Melinda Joyce Brown ,  Yusuf Cagatay Tekmen ,  Brian Michael Stempel ,  Michael Scott Mcilvaine ,  Thomas Philip Speier ,  Rodney Wayne Smith ,  Gagan Gupta ,  David Tennyson Harper, III

IPC分类号： G06F9/38

摘要： Operand-based reach explicit dataflow processors, and related methods and computer-readable media are disclosed. The operand-based reach explicit dataflow processors support execution of a producer instruction that explicitly names a target consumer operand of a consumer instruction in a consumer operand encoding namespace of the producer instruction. The produced value from execution of the producer instruction is provided or otherwise made available as an input to the named target consumer operand of the consumer instruction as a result of processing the producer instruction. The target consumer operand is encoded in the producer instruction as an operand target distance relative to the producer instruction. Instructions in an instruction stream between the producer instruction and the targeted consumer instruction that have no operands do not consume an operand reach namespace in the producer instructions. This provides for a deeper explicit consumer naming reach for a given bit size of the operand reach namespace.

公开(公告)号：US11803389B2

公开(公告)日：2023-10-31

申请号：US16738362

申请日：2020-01-09

申请人： Microsoft Technology Licensing, LLC

发明人： Yusuf Cagatay Tekmen ,  Rodney Wayne Smith ,  Douglas C. Burger ,  Gagan Gupta ,  Kiran Ravi Seth

IPC分类号： G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/3836

摘要： A reach matrix scheduler circuit for scheduling instructions to be executed in a processor is disclosed. The scheduler circuit includes an N×R matrix wake-up circuit, where ‘N’ is the instruction window size of the scheduler circuit, and ‘R’ is the “reach” within the instruction window of the matrix wake-up circuit, with ‘R’ being less than ‘N’. A grant line associated with each instruction request entry in the N×R matrix wake-up circuit is coupled to ‘R’ other instruction entries among the ‘N’ instruction entries. When a producer instruction in an instruction request entry is ready for issuance, the grant line associated with the instruction request entry is activated so that any other instruction entries coupled to the grant line (i.e., within the “reach” of the instruction request entry) that consume the produced value generated by the producer instruction are “woken-up” and subsequently indicated as ready to be issued.

公开(公告)号：US20180267807A1

公开(公告)日：2018-09-20

申请号：US15595582

申请日：2017-05-15

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas C. Burger ,  Gagan Gupta

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F15/78

CPC分类号： G06F9/3861 ,  G06F9/30116 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3865 ,  G06F9/4806 ,  G06F9/4812 ,  G06F15/76 ,  G06F15/7839 ,  G06F2209/481

摘要： Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes an exception event handler, a memory interface, at least one block-based processor core coupled to the memory interface and configured to responsive to receiving an exception event signal while executing an instruction block, store state data for the core generated by executing the instruction block, transfer control of the core to a second instruction block, and resume execution of the first instruction by restoring state for the processor core from the stored state data.

公开(公告)号：US11704253B2

公开(公告)日：2023-07-18

申请号：US17177775

申请日：2021-02-17

申请人： Microsoft Technology Licensing, LLC

发明人： Thomas Philip Speier ,  Jason S. Wohlgemuth ,  Artur Klauser ,  Gagan Gupta ,  Cody D. Hartwig ,  Abolade Gbadegesin

IPC分类号： G06F9/38 ,  G06F12/1081 ,  G06F12/1036 ,  G06F9/30 ,  G06F9/455 ,  G06F11/07 ,  G06F12/0882 ,  G06F12/1045

CPC分类号： G06F12/1036 ,  G06F9/3004 ,  G06F9/30079 ,  G06F9/30101 ,  G06F9/3842 ,  G06F9/45558 ,  G06F11/0772 ,  G06F12/0882 ,  G06F12/1054 ,  G06F12/1063 ,  G06F12/1081 ,  G06F2009/45583

摘要： Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address. In some embodiments, any address translation errors encountered are raised to an appropriate exception level, and may be raised synchronously or asynchronously with respect to an operation performed when the speculative translation instruction is executed.