公开(公告)号：US11016770B2

公开(公告)日：2021-05-25

申请号：US15044045

申请日：2016-02-15

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Aaron L. Smith

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F11/36 ,  G06F15/78 ,  G06F9/26 ,  G06F9/32 ,  G06F9/345 ,  G06F9/35 ,  G06F12/0806 ,  G06F12/0862 ,  G06F12/1009 ,  G06F13/42 ,  G06F15/80 ,  G06F9/355 ,  G06F12/0811 ,  G06F12/0875

Abstract: Distinct system registers for logical processors are disclosed. In one example of the disclosed technology, a processor includes a plurality of block-based physical processor cores for executing a program comprising a plurality of instruction blocks. The processor also includes a thread scheduler configured to schedule a thread of the program for execution, the thread using the one or more instruction blocks. The processor further includes at least one system register. The at least one system register stores data indicating a number and placement of the plurality of physical processor cores to form a logical processor. The logical processor executes the scheduled thread. The logical processor is configured to execute the thread in a continuous instruction window.

公开(公告)号：US10776115B2

公开(公告)日：2020-09-15

申请号：US14942557

申请日：2015-11-16

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Aaron L. Smith

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/52 ,  G06F11/36 ,  G06F9/26 ,  G06F9/32 ,  G06F9/345 ,  G06F9/35 ,  G06F12/0806 ,  G06F12/0862 ,  G06F12/1009 ,  G06F13/42 ,  G06F15/80 ,  G06F15/78 ,  G06F9/355 ,  G06F12/0811 ,  G06F12/0875

Abstract: Systems and methods are disclosed for supporting debugging of programs in block-based processor architectures. In one example of the disclosed technology, a processor includes a block-based processor core for executing an instruction block comprising an instruction header and a plurality of instructions. The block-based processor core includes execution control logic and core state access logic. The execution control logic can be configured to schedule respective instructions of the plurality of instructions for execution in a dynamic order during a default execution mode and to schedule the respective instructions for execution in a static order during a debug mode. The core state access logic can be configured to read intermediate states of the block-based processor core and to provide the intermediate states outside of the block-based processor core during the debug mode.

公开(公告)号：US10445097B2

公开(公告)日：2019-10-15

申请号：US15073365

申请日：2016-03-17

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Aaron L. Smith

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F9/32 ,  G06F9/26 ,  G06F11/36 ,  G06F12/0862 ,  G06F9/35 ,  G06F12/1009 ,  G06F13/42 ,  G06F12/0806 ,  G06F15/78 ,  G06F9/46 ,  G06F9/52 ,  G06F9/345 ,  G06F9/355 ,  G06F12/0875 ,  G06F12/0811

Abstract: Apparatus and methods are disclosed for decoding targets from an instruction and transmitting data to those targets in accordance with a current instruction. Multimodal target hardware is used in conjunction with one or more of the routers so as to route data to an appropriate target. The data can be one or more operands or a predicate and the targets can include operand buffers, broadcast channels, and general registers. In this way, operands, for example, can be directed for use with multiple subsequent instructions, and there are multiple modes for distributing the operands to the multiple instructions.

公开(公告)号：US10409606B2

公开(公告)日：2019-09-10

申请号：US14752356

申请日：2015-06-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Aaron L. Smith ,  Jan S. Gray

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: Apparatus and methods are disclosed for implementing bad jump detection in block-based processor architectures. In one example of the disclosed technology, a block-based processor includes one or more block-based processing cores configured to fetch and execute atomic blocks of instructions and a control unit configured to, based at least in part on receiving a branch signal indicating a target location is received from one of the instruction blocks, verify that the target location is a valid branch target.

公开(公告)号：US10095519B2

公开(公告)日：2018-10-09

申请号：US15060483

申请日：2016-03-03

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Aaron L. Smith

IPC: G06F9/355 ,  G06F15/80 ,  G06F12/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/26 ,  G06F11/36 ,  G06F12/0862 ,  G06F9/35 ,  G06F12/1009 ,  G06F13/42 ,  G06F15/78 ,  G06F9/46 ,  G06F9/52 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0806

Abstract: Apparatus and methods are disclosed for controlling instruction flow in block-based processor architectures. In one example of the disclosed technology, an instruction block address register stores an index address to a memory storing a plurality of instructions for an instruction block, the indexed address being inaccessible when the processor is in one or more unprivileged operational modes, one or more execution units configured to execute instructions for the instruction block, and a control unit configured to fetch and decode two or more of the plurality of instructions from the memory based on the indexed address.

公开(公告)号：US20170315815A1

公开(公告)日：2017-11-02

申请号：US15224624

申请日：2016-07-31

Applicant: Microsoft Technology Licensing, LLC

Inventor： Aaron L. Smith ,  Jan S. Gray

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3005 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3873 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3897 ,  G06F12/0875 ,  G06F15/7867

Abstract: Apparatus and methods are disclosed for implementing block-based processors having custom function blocks, including field-programmable gate array (FPGA) implementations. In some examples of the disclosed technology, a dynamically configurable scheduler is configured to issue at least one block-based processor instruction. A custom function block is configured to receive input operands for the instruction and generate ready state data indicating completion of a computation performed for the instruction by the respective custom function block.

公开(公告)号：US20170315813A1

公开(公告)日：2017-11-02

申请号：US15224473

申请日：2016-07-29

Applicant: Microsoft Technology Licensing, LLC

Inventor： Aaron L. Smith ,  Jan S. Gray

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3005 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3873 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3897 ,  G06F12/0875 ,  G06F15/7867

Abstract: Apparatus and methods are disclosed for implementing incremental schedulers for out-of-order block-based processors, including field programmable gate array implementations. In one example of the disclosed technology, a processor includes an instruction scheduler formed by configuring one or more look up table RAMs to store ready state data for a plurality of instructions in an instruction block. The instruction scheduler further includes a plurality of queues that store ready state data for the processor and sends dependency information to ready determination logic on a first in/first out basis. The instruction scheduler selects one or more of the ready instructions to be issued and executed by the block-based processor.

公开(公告)号：US20170315812A1

公开(公告)日：2017-11-02

申请号：US15224471

申请日：2016-07-29

Applicant: Microsoft Technology Licensing, LLC

Inventor： Aaron L. Smith ,  Jan S. Gray

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3005 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3873 ,  G06F9/3885 ,  G06F9/3889 ,  G06F9/3897 ,  G06F12/0875 ,  G06F15/7867

Abstract: Apparatus and methods are disclosed for implementing block-based processors, including field programmable gate-array (FPGA) implementations. In one example of the disclosed technology, an instruction decoder configured to generate ready state data for a set of instructions in an instruction block, each of the set of instructions being associated with a different instruction identifier encoded in the transactional block and a parallel instruction scheduler configured to issue an instruction from the set of instructions based on the decoded ready state data. In some examples, the parallel instruction scheduler allows for improved area and energy savings according to the size and type of FPGA components available.

公开(公告)号：US20170083326A1

公开(公告)日：2017-03-23

申请号：US15012662

申请日：2016-02-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Douglas C. Burger ,  Aaron L. Smith

IPC: G06F9/30 ,  G06F12/10 ,  G06F12/08

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for controlling execution of register access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of register access instruction in an instruction block. In one example of the disclosed technology, a method of operating a processor includes selecting a register access instruction of the plurality of instructions to execute based at least in part on dependencies encoded within a previous block of instructions and on stored data indicating which of the register write instructions have executed for the previous block, and executing the selected instruction. In some examples, one or more of a write mask, a read mask, a register write vector register, or a counter are used to determine register read/write dependences. Based on the encoded dependencies and the masked write vector, the next instruction block can issue when its register dependencies are available.

公开(公告)号：US20160378661A1

公开(公告)日：2016-12-29

申请号：US14752418

申请日：2015-06-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： Jan S. Gray ,  Douglas C. Burger ,  Aaron L. Smith

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/30 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3846 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3869 ,  G06F9/3891 ,  G06F11/30 ,  G06F12/128 ,  G06F2212/621

Abstract: Apparatus and methods are disclosed for throttling processor operation in block-based processor architectures. In one example of the disclosed technology, a block-based instruction set architecture processor includes a plurality of processing cores configured to fetch and execute a sequence of instruction blocks. Each of the processing cores includes function resources for performing operations specified by the instruction blocks. The processor further includes a core scheduler configured to allocate functional resources for performing the operations. The functional resources are allocated for executing the instruction blocks based, at least in part, on a performance metric. The performance metric can be generated dynamically or statically based on branch prediction accuracy, energy usage tolerance, and other suitable metrics.

Abstract translation: 公开了用于在基于块的处理器架构中节流处理器操作的装置和方法。 在所公开的技术的一个示例中，基于块的指令集架构处理器包括被配置为获取和执行指令块序列的多个处理核心。 每个处理核心包括用于执行由指令块指定的操作的功能资源。 处理器还包括被配置为分配用于执行操作的功能资源的核心调度器。 分配功能资源用于至少部分地基于性能指标来执行指令块。 可以基于分支预测精度，能量使用容忍度和其他合适的度量动态地或静态地生成性能度量。