公开(公告)号：US11062759B1

公开(公告)日：2021-07-13

申请号：US16837041

申请日：2020-04-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Cheng-Hsien Cheng ,  Atsuhiro Suzuki ,  Yu-Hung Huang ,  Sheng-Kai Chen ,  Wen-Jer Tsai

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/409 ,  G11C11/4076

Abstract: A memory device and a programming method thereof are provided. The memory device includes a memory array, a plurality of word lines and a voltage generator. During a programming procedure, one of the word lines is at a selected state and others of the word lines are at a deselected state. Some of the word lines, which are at the deselected state, are classified into a first group and a second group. The first group and the second group are respectively located at two sides of the word line, which is at the selected state. The voltage generator provides a programming voltage to the word line, which is at the select state, during a programming duration. The voltage generator provides a first two-stage voltage waveform to the word lines in the first group and provides a second two-stage voltage waveform to the word lines in the second group.

公开(公告)号：US20170025179A1

公开(公告)日：2017-01-26

申请号：US14808745

申请日：2015-07-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/24 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/10

Abstract: Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled to a bit line and word lines, the word lines arranged orthogonally to the NAND strings and establishing the memory cells at cross-points between surfaces of the NAND strings and the word lines, and a first set of discharge transistors positioned at an edge of the 3D array, coupled to a corresponding bit line, and configured for BL discharge, and a second set of discharge transistors positioned such that a first portion of BL potential is discharged through the first set of discharge transistors and a second portion through the second set.

Abstract translation: 本文中设想的方法和装置用于减少非易失性存储器件的位线恢复时间。 在示例性实施例中，非易失性存储器件包括非易失性存储器单元的3D阵列，包括多个块，每个块包括多个NAND串，每个NAND串耦合到位线和字线， 与NAND串正交排列的字线和在NAND串和字线的表面之间的交叉点建立存储单元，以及位于3D阵列边缘的第一组放电晶体管，耦合到相应的位线 并且被配置为用于BL放电，以及第二组放电晶体管，其定位成使得BL电位的第一部分通过第一组放电晶体管放电，并且通过第二组放电第二部分。

公开(公告)号：US10262748B1

公开(公告)日：2019-04-16

申请号：US15838109

申请日：2017-12-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee ,  Atsuhiro Suzuki

IPC: G11C16/34 ,  G11C16/10

Abstract: A non-volatile memory and a program method thereof are provided. The program method of the non-volatile memory includes: setting a first incremental value, and providing a plurality of first pulses of incrementally increasing voltages in sequence according to the first incremental value for performing a programming operation on a plurality of non-volatile memory cells during a first time period; and setting a second incremental value, and providing a plurality of second pulses of incrementally increasing voltages in sequence according to the second incremental value for performing a programming operation on the non-volatile memory cells during a second time period which is after the first time period, wherein the first incremental value is smaller than the second incremental value.

公开(公告)号：US09859007B2

公开(公告)日：2018-01-02

申请号：US14742054

申请日：2015-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.

公开(公告)号：US10340017B2

公开(公告)日：2019-07-02

申请号：US15803986

申请日：2017-11-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C8/14

Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

公开(公告)号：US09437319B1

公开(公告)日：2016-09-06

申请号：US14750065

申请日：2015-06-25

Applicant: Macronix International Co., Ltd.

Inventor： Atsuhiro Suzuki ,  Ya Jui Lee ,  Kuan Fu Chen ,  Chih-Wei Lee

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459 ,  G11C16/3481 ,  G11C16/3486

Abstract: Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.

Abstract translation: 提供了在编程非易失性存储器时减少位线干扰的方法，装置和/或类似装置。 一种方法包括提供包括一组单元的非易失性存储器件，每个单元与位线相关联; 拍摄每个单元格上的编程电压; 检测每个单元的阈值电压; 至少部分地基于每个单元的检测到的阈值电压来识别该组单元的快速子集和该组单元的慢子集; 并拍摄编程电压，直到每个单元的阈值电压大于验证电压。 对于每个镜头，快速位线偏置被施加到与快速子集的每个单元相关联的位线，并且慢位线偏置被施加到与慢子集的每个单元相关联的位线。

公开(公告)号：US11037632B1

公开(公告)日：2021-06-15

申请号：US16828997

申请日：2020-03-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Chih-Chieh Cheng ,  Cheng-Hsien Cheng ,  Yu-Hung Huang ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.

公开(公告)号：US20160372202A1

公开(公告)日：2016-12-22

申请号：US14742054

申请日：2015-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Atsuhiro Suzuki ,  Chih-Wei Lee ,  Shaw-Hung Ku

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.

Abstract translation: 本文中设想的方法和装置用于增强非易失性存储器件的程序性能。 在示例实施例中，非易失性存储器件包括包括多个层的非易失性存储器单元的3D阵列，每个层包括非易失性存储器单元的NAND串，耦合到位线的NAND串和多个SSL和字线， 所述SSL和所述字线与所述NAND串正交排列，所述字线在所述多个NAND串的表面和所述字线之间的交叉点处建立所述非易失性存储单元，所述NAND串中的每一个还包括多个SSL晶体管 将SSL耦合到NAND串，其中至少第一SSL被配置为接收第一电压，第二SSL被配置为在第二电压下接收，并且其中第二SSL更靠近字线。